[PATCH rdma-next v2 09/15] net/mlx5: Enable relaxed ordering on FW tracer mkey

[Michael Gur <michaelgur@nvidia.com>]

On HW that restricts strong ordering, mkey creation fails unless relaxed
ordering is set, which prevents the FW tracer from being enabled.

Set relaxed ordering on the FW tracer mkey only on such HW, to work
around this limitation. This has no effect on the ordering of the trace
data, as once the mkey is configured as the tracer output buffer, FW and
HW write to it with strong ordering regardless of the mkey ordering
attributes. Strong ordering is required by design, as the driver polls
the buffer and considers a block valid once its last bytes hold a valid
timestamp. Out of order writes could expose a partially written block
to the driver.

Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Michael Gur <michaelgur@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c
index 1493d8106c1a..003ba788dd4f 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c
@@ -208,6 +208,8 @@ static int mlx5_fw_tracer_create_mkey(struct mlx5_fw_tracer *tracer)
 		 DIV_ROUND_UP(TRACER_BUFFER_PAGE_NUM, 2));
 	MLX5_SET64(mkc, mkc, start_addr, tracer->buff.dma);
 	MLX5_SET64(mkc, mkc, len, tracer->buff.size);
+	if (MLX5_CAP_GEN(dev, mkc_order_write_after_write_ro_only))
+		mlx5_core_mkey_set_ordering(dev, mkc, MLX5_MKEY_ORDER_RELAXED);
 	err = mlx5_core_create_mkey(dev, &tracer->buff.mkey, in, inlen);
 	if (err)
 		mlx5_core_warn(dev, "FWTracer: Failed to create mkey, %d\n", err);
-- 
2.52.0