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Wed, 04 Nov 2026 07:19:33 -0800 (PST) Received: from lake ([2a02:810d:d09:1b65:4366:70cb:bf82:f8ac]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48fec8d8e29sm4639812f8f.19.2026.11.04.07.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 07:19:31 -0800 (PST) From: Christian Schmidbauer To: netdev@vger.kernel.org Cc: maxime.chevallier@bootlin.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, Oleksij Rempel , Christian Schmidbauer , stable@vger.kernel.org, Maxime Coquelin , Alexandre Torgue , Giuseppe Cavallaro , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 3/3] net: stmmac: dwmac1000: stop hardware from dropping checksum-error packets Date: Wed, 4 Nov 2026 16:19:13 +0100 Message-ID: <20261104151914.2651241-4-opensource@grische.xyz> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20261104151914.2651241-1-opensource@grische.xyz> References: <20261104151914.2651241-1-opensource@grische.xyz> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When the checksum offload engine (CoE) is enabled, the dwmac1000 MAC silently drops any frame for which the engine detects a checksum error, before the driver sees it. This breaks VXLAN over IPv6 with zero UDP checksums, which RFC 6935 and RFC 6936 allow for tunnels. Set DMA_CONTROL_DT so that such frames are delivered instead of dropped, as commit fe4042797651 ("net: stmmac: dwmac4: stop hardware from dropping checksum-error packets") did for dwmac4. CoE remains enabled, so the driver still sees the error status and marks the skb CHECKSUM_NONE for the stack to verify. Set the bit only with enhanced descriptors. The normal descriptor parser does not report a checksum-only error to the stack, so cores that use it keep dropping such frames in hardware anyway. Tested on an Aruba AP-325 (ipq806x-gmac-dwmac) with Rx checksum offload on. Link: https://lore.kernel.org/all/20250625132117.1b3264e8@kernel.org/ Link: https://github.com/freifunk-gluon/gluon/issues/3783 Fixes: 47dd7a540b8a ("net: add support for STMicroelectronics Ethernet controllers.") Cc: # 6.6.x: ee0aace5f844: net: stmmac: Correctly handle Rx checksum offload errors Cc: # 6.6.x Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Christian Schmidbauer --- Depends on patches 1 and 2 of this series. v2: - Set DMA_CONTROL_DT only with enhanced descriptors. The normal descriptor parser does not report a checksum-only error, so cores with normal descriptors and Type 2 CoE keep the hardware drop. v1: https://lore.kernel.org/netdev/20261020190319.884375-1-opensource@grische.xyz/ drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h index 1de1f929d61c..004e6e30a68b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h @@ -163,6 +163,7 @@ enum rx_tx_priority_ratio { /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ /* Disable Drop TCP/IP csum error */ +#define DMA_CONTROL_DT 0x04000000 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ /* Threshold for Activating the FC */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c index 3ac7a7949529..31d5f79ef560 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c @@ -15,6 +15,7 @@ #include #include "dwmac1000.h" #include "dwmac_dma.h" +#include "stmmac.h" static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) { @@ -129,6 +130,13 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv, { u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel)); + /* Deliver checksum-error frames only with enhanced + * descriptors, because the normal descriptor parser does not + * report a checksum-only error. + */ + if (priv->plat->enh_desc) + csr6 |= DMA_CONTROL_DT; + if (mode == SF_DMA_MODE) { pr_debug("GMAC: enable RX store and forward mode\n"); csr6 |= DMA_CONTROL_RSF | DMA_CONTROL_DFF; -- 2.54.0