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[93.34.90.148]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4b57317cb8esm59576355e9.13.2026.11.05.02.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 02:55:14 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , Joris Vaisvila , Ahmed Naseef , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v5 4/6] net: phy: mediatek: split Airoha code to dedicated source Date: Thu, 5 Nov 2026 11:55:00 +0100 Message-ID: <20261105105504.1024-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261105105504.1024-1-ansuelsmth@gmail.com> References: <20261105105504.1024-1-ansuelsmth@gmail.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In preparation for Airoha PHYs software calibration support, split the Airoha code to dedicated source following Mediatek naming pattern of "ge-soc". This is to tidy things up and not overload the mediatek driver of specific Airoha code and ship a bigger PHY kernel module with dead code. Move the shared LEDs function to mtk-phy-lib to permit the split instead of duplicating the code. Also add myself as MAINTAINER of the now new airoha-ge-soc driver. Signed-off-by: Christian Marangi Reviewed-by: Andrew Lunn --- MAINTAINERS | 8 ++ drivers/net/phy/mediatek/Kconfig | 18 ++- drivers/net/phy/mediatek/Makefile | 1 + drivers/net/phy/mediatek/airoha-ge-soc.c | 128 +++++++++++++++++ drivers/net/phy/mediatek/mtk-ge-soc.c | 172 ----------------------- drivers/net/phy/mediatek/mtk-ge-soc.h | 6 +- drivers/net/phy/mediatek/mtk-phy-lib.c | 72 ++++++++++ drivers/net/phy/mediatek/mtk.h | 12 ++ 8 files changed, 239 insertions(+), 178 deletions(-) create mode 100644 drivers/net/phy/mediatek/airoha-ge-soc.c diff --git a/MAINTAINERS b/MAINTAINERS index 8add8b8cd306..8a3e84d7eff3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -771,6 +771,14 @@ S: Maintained F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml F: drivers/net/ethernet/airoha/ +AIROHA ETHERNET PHY DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/phy/mediatek/airoha-ge-soc.c + AIROHA PCIE PHY DRIVER M: Lorenzo Bianconi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig index 3b9cf82c0cb2..5abf78202991 100644 --- a/drivers/net/phy/mediatek/Kconfig +++ b/drivers/net/phy/mediatek/Kconfig @@ -1,4 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only +config AIROHA_GE_SOC_PHY + tristate "Airoha SoC Gigabit Ethernet PHYs" + depends on ARM64 || ECONET || COMPILE_TEST + depends on ARCH_AIROHA || ECONET || COMPILE_TEST + select MTK_NET_PHYLIB + select PHY_PACKAGE + help + Supports Airoha SoC built-in Gigabit Ethernet PHYs. + + Include support for built-in Ethernet PHYs which are present in + the AN7581 and AN7583 SoCs. These PHYs will dynamically + calibrate during startup. + config MEDIATEK_2P5GE_PHY tristate "MediaTek 2.5Gb Ethernet PHYs" depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST @@ -32,9 +45,8 @@ config MEDIATEK_FE_SOC_PHY config MEDIATEK_GE_SOC_PHY tristate "MediaTek SoC Gigabit Ethernet PHYs" - depends on ARM64 || ECONET || COMPILE_TEST - depends on ARCH_AIROHA || (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || \ - ECONET || COMPILE_TEST + depends on ARM64 || COMPILE_TEST + depends on (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST select MTK_NET_PHYLIB select PHY_PACKAGE help diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile index 6f9cacf7f906..5594057f51d0 100644 --- a/drivers/net/phy/mediatek/Makefile +++ b/drivers/net/phy/mediatek/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_AIROHA_GE_SOC_PHY) += airoha-ge-soc.o obj-$(CONFIG_MEDIATEK_2P5GE_PHY) += mtk-2p5ge.o obj-$(CONFIG_MEDIATEK_FE_SOC_PHY) += mtk-fe-soc.o obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o diff --git a/drivers/net/phy/mediatek/airoha-ge-soc.c b/drivers/net/phy/mediatek/airoha-ge-soc.c new file mode 100644 index 000000000000..e40e4597cd94 --- /dev/null +++ b/drivers/net/phy/mediatek/airoha-ge-soc.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include + +#include "mtk.h" +#include "mtk-ge-soc.h" + +#define AIROHA_PHY_MAX_LEDS 2 + +static int an7581_phy_probe(struct phy_device *phydev) +{ + struct mtk_socphy_priv *priv; + struct pinctrl *pinctrl; + + /* Toggle pinctrl to enable PHY LED */ + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); + if (IS_ERR(pinctrl)) + dev_err(&phydev->mdio.bus->dev, + "Failed to setup PHY LED pinctrl\n"); + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return 0; +} + +static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, + unsigned long modes) +{ + u16 val = 0; + u32 mode; + + if (index >= AIROHA_PHY_MAX_LEDS) + return -EINVAL; + + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { + switch (mode) { + case PHY_LED_ACTIVE_LOW: + val = MTK_PHY_LED_ON_POLARITY; + break; + case PHY_LED_ACTIVE_HIGH: + break; + default: + return -EINVAL; + } + } + + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? + MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_POLARITY, val); +} + +static int en7528_phy_config_init(struct phy_device *phydev) +{ + /* The LED controller of the EN7528 powers up with its external + * control disabled, leaving the LED pins dark regardless of what is + * programmed into the LED control registers. Hand the pins over to + * the LED control registers the same way the air_en8811h driver + * does; the mode field of this register is already set out of reset. + */ + return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED_BCR, + MTK_PHY_LED_BCR_CLK_EN | + MTK_PHY_LED_BCR_EXT_CTRL); +} + +static int an7583_phy_config_init(struct phy_device *phydev) +{ + /* BMCR_PDOWN is enabled by default */ + return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); +} + +static struct phy_driver mtk_socphy_driver[] = { + { + PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_EN7528), + .name = "EcoNet EN7528 PHY", + .config_init = en7528_phy_config_init, + .probe = an7581_phy_probe, + .led_blink_set = mt798x_phy_led_blink_set, + .led_brightness_set = mt798x_phy_led_brightness_set, + .led_hw_is_supported = mt798x_phy_led_hw_is_supported, + .led_hw_control_set = mt798x_phy_led_hw_control_set, + .led_hw_control_get = mt798x_phy_led_hw_control_get, + .led_polarity_set = an7581_phy_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7581), + .name = "Airoha AN7581 PHY", + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .probe = an7581_phy_probe, + .led_blink_set = mt798x_phy_led_blink_set, + .led_brightness_set = mt798x_phy_led_brightness_set, + .led_hw_is_supported = mt798x_phy_led_hw_is_supported, + .led_hw_control_set = mt798x_phy_led_hw_control_set, + .led_hw_control_get = mt798x_phy_led_hw_control_get, + .led_polarity_set = an7581_phy_led_polarity_set, + }, + { + PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7583), + .name = "Airoha AN7583 PHY", + .config_init = an7583_phy_config_init, + .probe = an7581_phy_probe, + .led_blink_set = mt798x_phy_led_blink_set, + .led_brightness_set = mt798x_phy_led_brightness_set, + .led_hw_is_supported = mt798x_phy_led_hw_is_supported, + .led_hw_control_set = mt798x_phy_led_hw_control_set, + .led_hw_control_get = mt798x_phy_led_hw_control_get, + .led_polarity_set = an7581_phy_led_polarity_set, + }, +}; + +module_phy_driver(mtk_socphy_driver); + +static const struct mdio_device_id __maybe_unused airoha_socphy_tbl[] = { + { PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_EN7528) }, + { PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7581) }, + { PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7583) }, + { } +}; + +MODULE_DESCRIPTION("Airoha SoC Gigabit Ethernet PHY driver"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); + +MODULE_DEVICE_TABLE(mdio, airoha_socphy_tbl); diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c index 2b1e9923db98..239190678f6d 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -877,73 +877,6 @@ static int mt798x_phy_config_init(struct phy_device *phydev) return mt798x_phy_calibration(phydev); } -static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, - unsigned long *delay_on, - unsigned long *delay_off) -{ - bool blinking = false; - int err; - - err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); - if (err < 0) - return err; - - err = mtk_phy_hw_led_blink_set(phydev, index, blinking); - if (err) - return err; - - return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, - false); -} - -static int mt798x_phy_led_brightness_set(struct phy_device *phydev, - u8 index, enum led_brightness value) -{ - int err; - - err = mtk_phy_hw_led_blink_set(phydev, index, false); - if (err) - return err; - - return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, - (value != LED_OFF)); -} - -static const unsigned long supported_triggers = - BIT(TRIGGER_NETDEV_FULL_DUPLEX) | - BIT(TRIGGER_NETDEV_HALF_DUPLEX) | - BIT(TRIGGER_NETDEV_LINK) | - BIT(TRIGGER_NETDEV_LINK_10) | - BIT(TRIGGER_NETDEV_LINK_100) | - BIT(TRIGGER_NETDEV_LINK_1000) | - BIT(TRIGGER_NETDEV_RX) | - BIT(TRIGGER_NETDEV_TX); - -static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, - unsigned long rules) -{ - return mtk_phy_led_hw_is_supported(phydev, index, rules, - supported_triggers); -} - -static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, - unsigned long *rules) -{ - return mtk_phy_led_hw_ctrl_get(phydev, index, rules, - MTK_GPHY_LED_ON_SET, - MTK_GPHY_LED_RX_BLINK_SET, - MTK_GPHY_LED_TX_BLINK_SET); -}; - -static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, - unsigned long rules) -{ - return mtk_phy_led_hw_ctrl_set(phydev, index, rules, - MTK_GPHY_LED_ON_SET, - MTK_GPHY_LED_RX_BLINK_SET, - MTK_GPHY_LED_TX_BLINK_SET); -}; - static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) { struct mtk_socphy_shared *priv = phy_package_get_priv(phydev); @@ -1080,71 +1013,6 @@ static int mt7981_phy_probe(struct phy_device *phydev) return mt798x_phy_calibration(phydev); } -static int an7581_phy_probe(struct phy_device *phydev) -{ - struct mtk_socphy_priv *priv; - struct pinctrl *pinctrl; - - /* Toggle pinctrl to enable PHY LED */ - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); - if (IS_ERR(pinctrl)) - dev_err(&phydev->mdio.bus->dev, - "Failed to setup PHY LED pinctrl\n"); - - priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - phydev->priv = priv; - - return 0; -} - -static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, - unsigned long modes) -{ - u16 val = 0; - u32 mode; - - if (index >= MTK_PHY_MAX_LEDS) - return -EINVAL; - - for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { - switch (mode) { - case PHY_LED_ACTIVE_LOW: - val = MTK_PHY_LED_ON_POLARITY; - break; - case PHY_LED_ACTIVE_HIGH: - break; - default: - return -EINVAL; - } - } - - return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? - MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED_ON_POLARITY, val); -} - -static int an7583_phy_config_init(struct phy_device *phydev) -{ - /* BMCR_PDOWN is enabled by default */ - return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); -} - -static int en7528_phy_config_init(struct phy_device *phydev) -{ - /* The LED controller of the EN7528 powers up with its external - * control disabled, leaving the LED pins dark regardless of what is - * programmed into the LED control registers. Hand the pins over to - * the LED control registers the same way the air_en8811h driver - * does; the mode field of this register is already set out of reset. - */ - return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED_BCR, - MTK_PHY_LED_BCR_CLK_EN | - MTK_PHY_LED_BCR_EXT_CTRL); -} - static struct phy_driver mtk_socphy_driver[] = { { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), @@ -1180,43 +1048,6 @@ static struct phy_driver mtk_socphy_driver[] = { .led_hw_control_set = mt798x_phy_led_hw_control_set, .led_hw_control_get = mt798x_phy_led_hw_control_get, }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_EN7528), - .name = "EcoNet EN7528 PHY", - .config_init = en7528_phy_config_init, - .probe = an7581_phy_probe, - .led_blink_set = mt798x_phy_led_blink_set, - .led_brightness_set = mt798x_phy_led_brightness_set, - .led_hw_is_supported = mt798x_phy_led_hw_is_supported, - .led_hw_control_set = mt798x_phy_led_hw_control_set, - .led_hw_control_get = mt798x_phy_led_hw_control_get, - .led_polarity_set = an7581_phy_led_polarity_set, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581), - .name = "Airoha AN7581 PHY", - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, - .probe = an7581_phy_probe, - .led_blink_set = mt798x_phy_led_blink_set, - .led_brightness_set = mt798x_phy_led_brightness_set, - .led_hw_is_supported = mt798x_phy_led_hw_is_supported, - .led_hw_control_set = mt798x_phy_led_hw_control_set, - .led_hw_control_get = mt798x_phy_led_hw_control_get, - .led_polarity_set = an7581_phy_led_polarity_set, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583), - .name = "Airoha AN7583 PHY", - .config_init = an7583_phy_config_init, - .probe = an7581_phy_probe, - .led_blink_set = mt798x_phy_led_blink_set, - .led_brightness_set = mt798x_phy_led_brightness_set, - .led_hw_is_supported = mt798x_phy_led_hw_is_supported, - .led_hw_control_set = mt798x_phy_led_hw_control_set, - .led_hw_control_get = mt798x_phy_led_hw_control_get, - .led_polarity_set = an7581_phy_led_polarity_set, - }, }; module_phy_driver(mtk_socphy_driver); @@ -1224,9 +1055,6 @@ module_phy_driver(mtk_socphy_driver); static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_EN7528) }, - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) }, - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583) }, { } }; diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.h b/drivers/net/phy/mediatek/mtk-ge-soc.h index 008efd148a2c..bcc4d0a435ef 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.h +++ b/drivers/net/phy/mediatek/mtk-ge-soc.h @@ -7,9 +7,9 @@ #define MTK_GPHY_ID_MT7981 0x03a29461 #define MTK_GPHY_ID_MT7988 0x03a29481 -#define MTK_GPHY_ID_EN7528 0x03a29491 -#define MTK_GPHY_ID_AN7581 0x03a294c1 -#define MTK_GPHY_ID_AN7583 0xc0ff0420 +#define AIROHA_GPHY_ID_EN7528 0x03a29491 +#define AIROHA_GPHY_ID_AN7581 0x03a294c1 +#define AIROHA_GPHY_ID_AN7583 0xc0ff0420 #define MTK_EXT_PAGE_ACCESS 0x1f #define MTK_PHY_PAGE_STANDARD 0x0000 diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/mediatek/mtk-phy-lib.c index 3e4fb899a85b..dc4abd95d73f 100644 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c @@ -339,6 +339,78 @@ void mtk_phy_leds_state_init(struct phy_device *phydev) } EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init); +int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + bool blinking = false; + int err; + + err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); + if (err < 0) + return err; + + err = mtk_phy_hw_led_blink_set(phydev, index, blinking); + if (err) + return err; + + return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, + false); +} +EXPORT_SYMBOL_GPL(mt798x_phy_led_blink_set); + +int mt798x_phy_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + int err; + + err = mtk_phy_hw_led_blink_set(phydev, index, false); + if (err) + return err; + + return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, + (value != LED_OFF)); +} +EXPORT_SYMBOL_GPL(mt798x_phy_led_brightness_set); + +static const unsigned long supported_triggers = + BIT(TRIGGER_NETDEV_FULL_DUPLEX) | + BIT(TRIGGER_NETDEV_HALF_DUPLEX) | + BIT(TRIGGER_NETDEV_LINK) | + BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_RX) | + BIT(TRIGGER_NETDEV_TX); + +int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + return mtk_phy_led_hw_is_supported(phydev, index, rules, + supported_triggers); +} +EXPORT_SYMBOL_GPL(mt798x_phy_led_hw_is_supported); + +int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + return mtk_phy_led_hw_ctrl_get(phydev, index, rules, + MTK_GPHY_LED_ON_SET, + MTK_GPHY_LED_RX_BLINK_SET, + MTK_GPHY_LED_TX_BLINK_SET); +}; +EXPORT_SYMBOL_GPL(mt798x_phy_led_hw_control_get); + +int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + return mtk_phy_led_hw_ctrl_set(phydev, index, rules, + MTK_GPHY_LED_ON_SET, + MTK_GPHY_LED_RX_BLINK_SET, + MTK_GPHY_LED_TX_BLINK_SET); +}; +EXPORT_SYMBOL_GPL(mt798x_phy_led_hw_control_set); + MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common"); MODULE_AUTHOR("Sky Huang "); MODULE_AUTHOR("Daniel Golle "); diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h index 3565e39b96a8..bc46646a95fd 100644 --- a/drivers/net/phy/mediatek/mtk.h +++ b/drivers/net/phy/mediatek/mtk.h @@ -103,4 +103,16 @@ int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking); void mtk_phy_leds_state_init(struct phy_device *phydev); +int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off); +int mt798x_phy_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value); +int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules); +int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules); +int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules); + #endif /* _MTK_EPHY_H_ */ -- 2.55.0