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[83.233.221.133]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b664b165e9sm1095181a12.29.2026.11.06.14.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 14:54:07 -0800 (PST) From: Yongzhao Chen To: Christian Marangi Cc: Andrew Lunn , Stanislaw Pal , netdev@vger.kernel.org, Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King , Florian Fainelli , linux-kernel@vger.kernel.org, Ziyang Huang Subject: Re: [PATCH net-next v8 1/2] net: dsa: qca8k: let regmap serialize register access Date: Fri, 6 Nov 2026 23:54:02 +0100 Message-ID: <20261106225403.272212-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 In-Reply-To: <6aee175b.f01aa0c8.37eba4.18ea@mx.google.com> References: <20261104120130.48455-1-yongzhao.derek@gmail.com> <20261104120130.48455-2-yongzhao.derek@gmail.com> <6aca850a-ef67-4451-aaf2-977be884d1b0@lunn.ch> <6aee175b.f01aa0c8.37eba4.18ea@mx.google.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Ansuel,=0D =0D On Fri, Nov 06, 2026 at 07:07:19PM +0100, Christian Marangi wrote:=0D > Operation of the LED and on the port have their own dedicated register pe= r=0D > port and for shared stuff, there is a dedicated mutex for it.=0D >=0D > So I'm not sure what case this patch is fixing...=0D =0D Stanislaw has walked through the regmap path. I can add a reproduction=0D of it in which the two accesses read different registers.=0D =0D It is a local KUnit test on UML. It builds qca8k-8xxx.c with the real=0D regmap_config, register callbacks, PCS and MTU code against the real=0D regmap core; only the MDIO bus below the driver is a fake register=0D file. The test stops one access inside its MDIO read and resumes it=0D once a second access has started and blocked, so the second access runs=0D between the first one's ->read() callback and its parse_val().=0D =0D With two qca8k_pcs_get_state() calls, for port 6 and port 0, each=0D reading its own PORT_STATUS register, port 6 returns port 0's link=0D state. Separate registers do not help, because both reads format the=0D register and return the value through the one map->work_buf.=0D =0D A second case runs the MTU code against a PCS poll. The PORT_STATUS=0D value that 2/2 saves is replaced, and MAX_FRAME_SIZE is written while a=0D CPU MAC is enabled. 2/2 relies on 1/2 for this, because readers such as=0D the PCS poll do not take its new mutex.=0D =0D On net-next, both cases fail with only 2/2 applied and pass with 1/2=0D added.=0D =0D The limits: the test forces the interleaving (a gate in the fake bus=0D and a SCHED_FIFO thread on a single-CPU UML kernel), it covers only the=0D MDIO path, not the management frames, and I have not seen the=0D corruption on hardware. The test calls qca8k_pcs_get_state() directly,=0D so it does not show that two PCS polls meet on a given board; the=0D callers that can meet without rtnl are the ones Stanislaw listed.=0D =0D The test is not part of the series. I can post it if that helps.=0D =0D If this answers what the patch fixes, I would keep 1/2 as is in v9 and=0D add the two-reader case to its commit message. Would you rather see a=0D different fix?=0D =0D Thanks,=0D Yongzhao Chen=0D