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[144.49.247.13]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-3b1278ae657sm1081690a91.4.2026.11.07.22.53.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 07 Nov 2026 22:53:01 -0800 (PST) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-dl1-f71.google.com with SMTP id a92af1059eb24-1aa0fb7f157so315179c88.0 for ; Sat, 07 Nov 2026 22:53:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1794120779; x=1794725579; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Evz3I6LRpPLttnyjUpSE785eEKCoczDe3Gc2UwvLma0=; b=Kj7R5BTRBiQrz5v3AhmHsXePe/fEGL4FFQGttl8IDv20T4h9zqmUbO4wTKo9J7bgoq BBY4LOUVDLh+tEPS2ZD+jSyjVFLy/2t5K4Oi6X6PvKLMVuHUcMxfvqMcBp3YDU74O/ek OhA/6Tf86UB4cdoJrpEpMxgyM4RpWLF1S94tA= X-Forwarded-Encrypted: i=1; AKwUvBy085oPE2btsnIsYZeB2o27lXgoLc3PFlnbSLLb2ybOuUDGOheKNNpp2WC7IMPY+8KwSuEs5L4=@vger.kernel.org X-Received: by 2002:a05:7022:ec17:b0:1ab:faad:cba with SMTP id a92af1059eb24-1b39fefeab3mr1384235c88.34.1794120779430; Sat, 07 Nov 2026 22:52:59 -0800 (PST) X-Received: by 2002:a05:7022:ec17:b0:1ab:faad:cba with SMTP id a92af1059eb24-1b39fefeab3mr1384208c88.34.1794120778721; Sat, 07 Nov 2026 22:52:58 -0800 (PST) Received: from pc-hpe-top-git-sendmail-server.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b3755e8a27sm3497993c88.7.2026.11.07.22.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Nov 2026 22:52:57 -0800 (PST) From: Pavan Chebbi To: michael.chan@broadcom.com, kuba@kernel.org Cc: andrew+netdev@lunn.ch, andrew.gospodarek@broadcom.com, davem@davemloft.net, edumazet@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, Pavan Chebbi , Somnath Kotur , Kalesh AP Subject: [PATCH net 2/4] tg3: Select PLL clock when preparing for shutdown Date: Sun, 8 Nov 2026 12:25:24 +0530 Message-ID: <20261108065526.710152-3-pavan.chebbi@broadcom.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20261108065526.710152-1-pavan.chebbi@broadcom.com> References: <20261108065526.710152-1-pavan.chebbi@broadcom.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e When the 5720 was linked up at 1G, it may fail to wake up on a single Magic packet. This is a hardware issue, which can be avoided by locking the PLL clock source before shutdown. When preparing for power down with Wake-on-LAN enabled, if the link was up at 1G, set CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL in TG3_CPMU_PLL_CTRL_STAT, so that the NCSI PLL locks on the TLP clock. The setting is cleared on the next chip reset. This was reported by a user, who confirmed that this change fixes it. Fixes: ba1f3c76d760 ("tg3: Enable 5720 support") Reviewed-by: Somnath Kotur Reviewed-by: Kalesh AP Signed-off-by: Pavan Chebbi --- drivers/net/ethernet/broadcom/tg3.c | 14 ++++++++++++++ drivers/net/ethernet/broadcom/tg3.h | 6 +++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 2cf9d2ea069b..e9b48e58fdd4 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -4127,6 +4127,14 @@ static void tg3_power_down_prepare(struct tg3 *tp) if (device_should_wake) { u32 mac_mode; + if (tg3_asic_rev(tp) == ASIC_REV_5720 && + tp->link_config.active_speed == SPEED_1000) { + u32 val = tr32(TG3_CPMU_PLL_CTRL_STAT); + + tw32(TG3_CPMU_PLL_CTRL_STAT, + val | CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL); + } + if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { if (do_low_power && !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { @@ -9394,6 +9402,12 @@ static int tg3_chip_reset(struct tg3 *tp) tg3_restore_clk(tp); + if (tg3_asic_rev(tp) == ASIC_REV_5720) { + val = tr32(TG3_CPMU_PLL_CTRL_STAT); + tw32(TG3_CPMU_PLL_CTRL_STAT, + val & ~CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL); + } + /* Increase the core clock speed to fix tx timeout issue for 5762 * with 100Mbps link speed. */ diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index a9e7f88fa26d..631bacc515ab 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -1168,7 +1168,11 @@ #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 -/* 0x3634 --> 0x365c unused */ +/* 0x3634 unused */ + +#define TG3_CPMU_PLL_CTRL_STAT 0x00003638 +#define CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL 0x04000000 +/* 0x363c --> 0x365c unused */ #define TG3_CPMU_MUTEX_REQ 0x0000365c #define CPMU_MUTEX_REQ_DRIVER 0x00001000 -- 2.52.0