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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Michal Schmidt , Jakub Ramaseuski , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH net 0/2] ice: dpll: fix updates of the SyncE CGU registers on E825 Date: Tue, 10 Nov 2026 10:43:48 +0100 Message-ID: <20261110094350.184185-1-ivecera@redhat.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.6 on 10.30.177.95 All E825C PFs share the CGU registers R10 and R11, which hold the mux and the divider of the two recovered clock outputs. Both patches fix how a link change updates them, both found in review: - Patch 1 adds a lock shared by all PFs around the read-modify-write sequences of these registers. A link change on one PF could undo an RCLK pin change made by another PF. - Patch 2 lets a link change set the divider of an output only when its port drives that output. Every port set it from its own link speed, which is wrong when ports run at different speeds. Both were tested on GNR-D with dual complex E825, details are in the commit messages. Patch 1 was also patch 2 of the net-next series "dpll: do not serialize driver callbacks under global dpll_lock" [1], which needs it. v2 of that series will drop it. [1] https://lore.kernel.org/netdev/20261106121005.1327603-1-ivecera@redhat.com/ Ivan Vecera (2): ice: dpll: serialize changes of the SyncE CGU registers ice: dpll: set the SyncE divider only for the port driving the output drivers/net/ethernet/intel/ice/ice_adapter.c | 2 ++ drivers/net/ethernet/intel/ice/ice_adapter.h | 4 ++++ drivers/net/ethernet/intel/ice/ice_dpll.c | 11 ++++++----- drivers/net/ethernet/intel/ice/ice_dpll.h | 4 ++++ drivers/net/ethernet/intel/ice/ice_ptp.c | 8 +++++++- drivers/net/ethernet/intel/ice/ice_tspll.c | 8 ++++---- 6 files changed, 27 insertions(+), 10 deletions(-) base-commit: 1d5e2c57e9ffc134e14b3f837c8d7c53b508bd22 -- 2.56.0