[PATCH net v2 2/4] tg3: Select PLL clock when preparing for shutdown

[Pavan Chebbi <pavan.chebbi@broadcom.com>]

When the 5720 was linked up at 1G before power down, it may fail to
wake up on a single Magic packet.  This is a hardware issue, which can
be avoided by locking the PLL clock source before shutdown.

On system suspend or power off with Wake-on-LAN enabled, if the last
link speed recorded before power down was 1G, set
CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL in TG3_CPMU_PLL_CTRL_STAT, so that the
NCSI PLL locks on the TLP clock.  The setting is cleared on resume and
at probe.

This was reported by a user, who confirmed that this change fixes it.

Fixes: ba1f3c76d760 ("tg3: Enable 5720 support")
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
---
 drivers/net/ethernet/broadcom/tg3.c | 35 +++++++++++++++++++++++++++++
 drivers/net/ethernet/broadcom/tg3.h |  6 ++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 2cf9d2ea069b..98338c0792e8 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -4267,8 +4267,38 @@ static void tg3_power_down_prepare(struct tg3 *tp)
 	return;
 }
 
+static void tg3_ncsi_pll_tlp_clk(struct tg3 *tp, bool enable)
+{
+	u32 val;
+
+	if (tg3_asic_rev(tp) != ASIC_REV_5720)
+		return;
+
+	/* The register is shared by both functions of the device. */
+	if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
+		return;
+
+	val = tr32(TG3_CPMU_PLL_CTRL_STAT);
+	if (enable)
+		val |= CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL;
+	else
+		val &= ~CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL;
+	tw32(TG3_CPMU_PLL_CTRL_STAT, val);
+
+	tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
+}
+
+static void tg3_wol_select_pll_clk(struct tg3 *tp)
+{
+	if (device_may_wakeup(&tp->pdev->dev) &&
+	    tg3_flag(tp, WOL_ENABLE) &&
+	    tp->link_config.active_speed == SPEED_1000)
+		tg3_ncsi_pll_tlp_clk(tp, true);
+}
+
 static void tg3_power_down(struct tg3 *tp)
 {
+	tg3_wol_select_pll_clk(tp);
 	pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
 	pci_set_power_state(tp->pdev, PCI_D3hot);
 }
@@ -17886,6 +17916,8 @@ static int tg3_init_one(struct pci_dev *pdev,
 		goto err_out_apeunmap;
 	}
 
+	tg3_ncsi_pll_tlp_clk(tp, false);
+
 	/* The EPB bridge inside 5714, 5715, and 5780 and any
 	 * device behind the EPB cannot support DMA addresses > 40-bit.
 	 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
@@ -18222,6 +18254,7 @@ static int tg3_suspend(struct device *device)
 	tg3_full_unlock(tp);
 
 	tg3_power_down_prepare(tp);
+	tg3_wol_select_pll_clk(tp);
 
 unlock:
 	rtnl_unlock();
@@ -18241,6 +18274,8 @@ static int tg3_resume(struct device *device)
 
 	netif_device_attach(dev);
 
+	tg3_ncsi_pll_tlp_clk(tp, false);
+
 	netdev_lock(dev);
 	tg3_full_lock(tp, 0);
 
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index a9e7f88fa26d..631bacc515ab 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1168,7 +1168,11 @@
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5	 0x00000000
 #define  CPMU_CLCK_STAT_MAC_CLCK_12_5	 0x00110000
 #define  CPMU_CLCK_STAT_MAC_CLCK_6_25	 0x00130000
-/* 0x3634 --> 0x365c unused */
+/* 0x3634 unused */
+
+#define TG3_CPMU_PLL_CTRL_STAT		0x00003638
+#define  CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL	0x04000000
+/* 0x363c --> 0x365c unused */
 
 #define TG3_CPMU_MUTEX_REQ		0x0000365c
 #define  CPMU_MUTEX_REQ_DRIVER		 0x00001000
-- 
2.52.0