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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH net-next v4 11/14] dpll: dpllsim: Add support to adjust phase Date: Thu, 12 Nov 2026 14:03:56 +0100 Message-ID: <20261112130359.840795-12-poros@redhat.com> In-Reply-To: <20261112130359.840795-1-poros@redhat.com> References: <20261112130359.840795-1-poros@redhat.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Add support to get and set the phase adjustment of input and output pins. The pins advertise a granularity of 100 ps and a symmetric range whose ends are the largest multiples of the granularity that fit a 32-bit signed value, so that the advertised ends themselves are settable, the core validates the requested value against both and the driver stores it. The adjustment is reset to zero every time the device goes live, so that repeated deploy cycles start from a known state. It becomes the baseline of the simulated phase offset measurements once those exist. Reviewed-by: Ivan Vecera Acked-by: Jiri Pirko Signed-off-by: Petr Oros --- drivers/dpll/dpllsim/dpll.c | 40 ++++++++++++++++++++++++++++++++++ drivers/dpll/dpllsim/dpllsim.h | 1 + 2 files changed, 41 insertions(+) diff --git a/drivers/dpll/dpllsim/dpll.c b/drivers/dpll/dpllsim/dpll.c index 0cce8fef232cd3..0260bffd157000 100644 --- a/drivers/dpll/dpllsim/dpll.c +++ b/drivers/dpll/dpllsim/dpll.c @@ -12,6 +12,11 @@ #include "dpllsim.h" +#define DPLLSIM_PHASE_ADJUST_GRAN 100 /* ps */ +/* Largest multiple of the granularity, so the range ends are settable */ +#define DPLLSIM_PHASE_ADJUST_MAX \ + (S32_MAX - S32_MAX % DPLLSIM_PHASE_ADJUST_GRAN) + static struct dpll_pin_frequency dpllsim_freq_1pps[] = { DPLL_PIN_FREQUENCY_RANGE(1, 1), }; @@ -182,6 +187,33 @@ static int dpllsim_pin_prio_set(const struct dpll_pin *pin, void *pin_priv, return 0; } +static int dpllsim_pin_phase_adjust_get(const struct dpll_pin *pin, + void *pin_priv, + const struct dpll_device *dpll, + void *dpll_priv, s32 *phase_adjust, + struct netlink_ext_ack *extack) +{ + struct dpllsim_pin *sim_pin = pin_priv; + + guard(mutex)(&sim_pin->dev->lock); + *phase_adjust = sim_pin->phase_adjust; + return 0; +} + +static int dpllsim_pin_phase_adjust_set(const struct dpll_pin *pin, + void *pin_priv, + const struct dpll_device *dpll, + void *dpll_priv, + const s32 phase_adjust, + struct netlink_ext_ack *extack) +{ + struct dpllsim_pin *sim_pin = pin_priv; + + guard(mutex)(&sim_pin->dev->lock); + sim_pin->phase_adjust = phase_adjust; + return 0; +} + static const struct dpll_pin_ops dpllsim_input_pin_ops = { .frequency_get = dpllsim_pin_frequency_get, .frequency_set = dpllsim_pin_frequency_set, @@ -190,6 +222,8 @@ static const struct dpll_pin_ops dpllsim_input_pin_ops = { .state_on_dpll_set = dpllsim_pin_state_set, .prio_get = dpllsim_pin_prio_get, .prio_set = dpllsim_pin_prio_set, + .phase_adjust_get = dpllsim_pin_phase_adjust_get, + .phase_adjust_set = dpllsim_pin_phase_adjust_set, }; static const struct dpll_pin_ops dpllsim_output_pin_ops = { @@ -197,6 +231,8 @@ static const struct dpll_pin_ops dpllsim_output_pin_ops = { .frequency_set = dpllsim_pin_frequency_set, .direction_get = dpllsim_pin_direction_get, .state_on_dpll_get = dpllsim_pin_state_get, + .phase_adjust_get = dpllsim_pin_phase_adjust_get, + .phase_adjust_set = dpllsim_pin_phase_adjust_set, }; static const struct dpll_pin_ops * @@ -212,6 +248,9 @@ static void dpllsim_pin_props(struct dpllsim_pin *pin, { prop->type = pin->type; prop->board_label = config_item_name(&pin->item); + prop->phase_range.min = -DPLLSIM_PHASE_ADJUST_MAX; + prop->phase_range.max = DPLLSIM_PHASE_ADJUST_MAX; + prop->phase_gran = DPLLSIM_PHASE_ADJUST_GRAN; switch (pin->type) { case DPLL_PIN_TYPE_GNSS: @@ -275,6 +314,7 @@ static void dpllsim_pin_reset(struct dpllsim_pin *pin) pin->state = DPLL_PIN_STATE_DISCONNECTED; pin->frequency = pin->cfg_frequency; pin->prio = pin->cfg_prio; + pin->phase_adjust = 0; } /* Build sim->pins in registration order, the order the pins were created */ diff --git a/drivers/dpll/dpllsim/dpllsim.h b/drivers/dpll/dpllsim/dpllsim.h index cd99227f1e4e1d..94383e71d7fcec 100644 --- a/drivers/dpll/dpllsim/dpllsim.h +++ b/drivers/dpll/dpllsim/dpllsim.h @@ -45,6 +45,7 @@ struct dpllsim_pin { */ u64 frequency; u32 prio; + s32 phase_adjust; }; struct dpllsim_dev { -- 2.56.0