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From: Petr Oros <poros@redhat.com>
To: netdev@vger.kernel.org
Cc: Petr Oros <poros@redhat.com>, Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	Jani Nikula <jani.nikula@intel.com>,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Jiri Pirko <jiri@resnulli.us>, Ivan Vecera <ivecera@redhat.com>,
	Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@kernel.org>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: [PATCH net-next v4 07/14] dpll: dpllsim: Add support to get/set priority on input pins
Date: Thu, 12 Nov 2026 14:03:52 +0100	[thread overview]
Message-ID: <20261112130359.840795-8-poros@redhat.com> (raw)
In-Reply-To: <20261112130359.840795-1-poros@redhat.com>

Add support for getting and setting the priority of input pins.
Implement the prio_get and prio_set callbacks and advertise the
priority-can-change capability for input pins, which includes the MUX
type pins since those are always inputs.

The initial priority of a pin is configured through a new prio
attribute of the pin directory, which takes a value between 0 and 255
and defaults to 128, so that a test can lay out the reference order
before the device goes live. Like the other pin attributes it is
writable only while the device is not live. Priority changes made over
netlink are stored and reported back, the driver does not select a
reference by them. They are kept apart from the configured value, so
that every live transition starts from what configfs holds, like the
pin state does, and the attribute keeps showing what was configured.
The setter rejects a value above 255 with EINVAL and an extack message.
A priority is meaningful for input pins only, so live fails with EINVAL
when an output pin was given a priority other than the default, next
to the frequency validation.

Signed-off-by: Petr Oros <poros@redhat.com>
---
v4:
- keep the priority set over netlink apart from the configured one,
  every live transition starts from the configured value and the
  attribute keeps showing it
- document that, and that the driver only stores the priority
- the Reviewed-by and Acked-by of v3 are not carried over, the
  behaviour of the driver changed

v3: https://lore.kernel.org/all/20261109093523.931201-8-poros@redhat.com/
---
 Documentation/driver-api/dpllsim.rst | 15 +++++++--
 drivers/dpll/dpllsim/core.c          | 31 +++++++++++++++++++
 drivers/dpll/dpllsim/dpll.c          | 46 ++++++++++++++++++++++++++--
 drivers/dpll/dpllsim/dpllsim.h       |  6 ++++
 4 files changed, 94 insertions(+), 4 deletions(-)

diff --git a/Documentation/driver-api/dpllsim.rst b/Documentation/driver-api/dpllsim.rst
index a0e5ea44d2c6d3..27cfc4b2c71518 100644
--- a/Documentation/driver-api/dpllsim.rst
+++ b/Documentation/driver-api/dpllsim.rst
@@ -37,6 +37,8 @@ Pin directory ``/sys/kernel/config/dpllsim/<dev>/pins/<pin>/``:
                (default 0, which is rejected)
 ``direction``  ``input`` or ``output`` (default ``input``), a ``mux`` pin
                must be an input
+``prio``       Initial priority 0-255 of an input pin, output pins must
+               keep the default (default 128)
 =============  ===============================================================
 
 The pin directory name becomes the board label of the pin. Pins are
@@ -55,8 +57,15 @@ The frequencies a pin type supports:
 
 The pin configuration is checked when 1 is written to ``live``. The
 write fails with ``EINVAL`` when a pin has a frequency its type does not
-support or when a ``mux`` pin is an output, and with ``ENOENT`` when a
-pin directory is being created or removed at the same time.
+support, when a ``mux`` pin is an output or when an output pin has a
+priority other than the default, and with ``ENOENT`` when a pin
+directory is being created or removed at the same time.
+
+Every live transition starts from the configured values. A priority set
+over netlink while the instance is live is reported back over netlink,
+it is not written to the ``prio`` attribute and is gone once the
+instance is taken down. The driver stores the priority, it does not
+select a reference by it.
 
 Example
 =======
@@ -70,8 +79,10 @@ output, then make it live::
     mkdir pins/gnss0
     echo gnss > pins/gnss0/type
     echo 1 > pins/gnss0/frequency
+    echo 0 > pins/gnss0/prio
     mkdir pins/ext0
     echo 10000000 > pins/ext0/frequency
+    echo 1 > pins/ext0/prio
     mkdir pins/out0
     echo 10000000 > pins/out0/frequency
     echo output > pins/out0/direction
diff --git a/drivers/dpll/dpllsim/core.c b/drivers/dpll/dpllsim/core.c
index 21c56aa4ecf5ac..fca16ec0976684 100644
--- a/drivers/dpll/dpllsim/core.c
+++ b/drivers/dpll/dpllsim/core.c
@@ -132,10 +132,40 @@ static ssize_t dpllsim_pin_frequency_store(struct config_item *item,
 }
 CONFIGFS_ATTR(dpllsim_pin_, frequency);
 
+static ssize_t dpllsim_pin_prio_show(struct config_item *item, char *page)
+{
+	struct dpllsim_pin *pin = to_dpllsim_pin(item);
+
+	guard(mutex)(&pin->dev->lock);
+	return sysfs_emit(page, "%u\n", pin->cfg_prio);
+}
+
+static ssize_t dpllsim_pin_prio_store(struct config_item *item,
+				      const char *page, size_t count)
+{
+	struct dpllsim_pin *pin = to_dpllsim_pin(item);
+	u32 val;
+	int err;
+
+	err = kstrtou32(page, 10, &val);
+	if (err)
+		return err;
+	if (val > DPLLSIM_PIN_PRIO_MAX)
+		return -EINVAL;
+
+	guard(mutex)(&pin->dev->lock);
+	if (dpllsim_dev_frozen(pin->dev))
+		return -EBUSY;
+	pin->cfg_prio = val;
+	return count;
+}
+CONFIGFS_ATTR(dpllsim_pin_, prio);
+
 static struct configfs_attribute *dpllsim_pin_attrs[] = {
 	&dpllsim_pin_attr_type,
 	&dpllsim_pin_attr_direction,
 	&dpllsim_pin_attr_frequency,
+	&dpllsim_pin_attr_prio,
 	NULL,
 };
 
@@ -178,6 +208,7 @@ static struct config_item *dpllsim_pins_make_item(struct config_group *group,
 	pin->dev = sim;
 	pin->type = DPLL_PIN_TYPE_EXT;
 	pin->direction = DPLL_PIN_DIRECTION_INPUT;
+	pin->cfg_prio = DPLLSIM_DEFAULT_PIN_PRIO;
 	list_add_tail(&pin->list, &sim->pin_list);
 
 	return &pin->item;
diff --git a/drivers/dpll/dpllsim/dpll.c b/drivers/dpll/dpllsim/dpll.c
index 794020d0c112e8..9fdb5dbeba4400 100644
--- a/drivers/dpll/dpllsim/dpll.c
+++ b/drivers/dpll/dpllsim/dpll.c
@@ -139,11 +139,43 @@ static int dpllsim_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
 	return 0;
 }
 
+static int dpllsim_pin_prio_get(const struct dpll_pin *pin, void *pin_priv,
+				const struct dpll_device *dpll,
+				void *dpll_priv, u32 *prio,
+				struct netlink_ext_ack *extack)
+{
+	struct dpllsim_pin *sim_pin = pin_priv;
+
+	guard(mutex)(&sim_pin->dev->lock);
+	*prio = sim_pin->prio;
+	return 0;
+}
+
+static int dpllsim_pin_prio_set(const struct dpll_pin *pin, void *pin_priv,
+				const struct dpll_device *dpll,
+				void *dpll_priv, u32 prio,
+				struct netlink_ext_ack *extack)
+{
+	struct dpllsim_pin *sim_pin = pin_priv;
+
+	if (prio > DPLLSIM_PIN_PRIO_MAX) {
+		NL_SET_ERR_MSG_FMT(extack, "Pin priority must be in range 0-%u",
+				   DPLLSIM_PIN_PRIO_MAX);
+		return -EINVAL;
+	}
+
+	guard(mutex)(&sim_pin->dev->lock);
+	sim_pin->prio = prio;
+	return 0;
+}
+
 static const struct dpll_pin_ops dpllsim_input_pin_ops = {
 	.frequency_get = dpllsim_pin_frequency_get,
 	.direction_get = dpllsim_pin_direction_get,
 	.state_on_dpll_get = dpllsim_pin_state_get,
 	.state_on_dpll_set = dpllsim_pin_state_set,
+	.prio_get = dpllsim_pin_prio_get,
+	.prio_set = dpllsim_pin_prio_set,
 };
 
 static const struct dpll_pin_ops dpllsim_output_pin_ops = {
@@ -188,7 +220,8 @@ static void dpllsim_pin_props(struct dpllsim_pin *pin,
 
 	/* Capabilities follow the ops the pin is served by */
 	if (dpllsim_pin_select_ops(pin) == &dpllsim_input_pin_ops)
-		prop->capabilities = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
+		prop->capabilities = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE |
+				     DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
 	else
 		prop->capabilities = 0;
 }
@@ -214,10 +247,18 @@ static bool dpllsim_pin_direction_valid(const struct dpllsim_pin *pin)
 	       pin->direction == DPLL_PIN_DIRECTION_INPUT;
 }
 
+/* Priority is meaningful for input pins only */
+static bool dpllsim_pin_prio_valid(const struct dpllsim_pin *pin)
+{
+	return pin->direction == DPLL_PIN_DIRECTION_INPUT ||
+	       pin->cfg_prio == DPLLSIM_DEFAULT_PIN_PRIO;
+}
+
 static void dpllsim_pin_reset(struct dpllsim_pin *pin)
 {
 	pin->ops = dpllsim_pin_select_ops(pin);
 	pin->state = DPLL_PIN_STATE_DISCONNECTED;
+	pin->prio = pin->cfg_prio;
 }
 
 /* Build sim->pins in registration order, the order the pins were created */
@@ -228,7 +269,8 @@ static int dpllsim_order_pins(struct dpllsim_dev *sim)
 
 	list_for_each_entry(pin, &sim->pin_list, list) {
 		if (!dpllsim_pin_frequency_valid(pin) ||
-		    !dpllsim_pin_direction_valid(pin))
+		    !dpllsim_pin_direction_valid(pin) ||
+		    !dpllsim_pin_prio_valid(pin))
 			return -EINVAL;
 		count++;
 	}
diff --git a/drivers/dpll/dpllsim/dpllsim.h b/drivers/dpll/dpllsim/dpllsim.h
index 73b846b66f79c7..54f4f1636f64e4 100644
--- a/drivers/dpll/dpllsim/dpllsim.h
+++ b/drivers/dpll/dpllsim/dpllsim.h
@@ -12,6 +12,9 @@
 #include <linux/list.h>
 #include <linux/mutex.h>
 
+#define DPLLSIM_DEFAULT_PIN_PRIO		128
+#define DPLLSIM_PIN_PRIO_MAX			255
+
 #define DPLLSIM_MAX_PINS			128
 
 struct dpllsim_dev;
@@ -25,6 +28,7 @@ struct dpllsim_pin {
 	enum dpll_pin_type type;
 	enum dpll_pin_direction direction;
 	u64 frequency;
+	u32 cfg_prio;
 
 	/* Resolved at live=1 */
 	int idx;
@@ -35,6 +39,8 @@ struct dpllsim_pin {
 
 	/* Simulated state, guarded by dev->lock */
 	enum dpll_pin_state state;
+	/* Starts from cfg_prio at live=1, changed by the netlink setter */
+	u32 prio;
 };
 
 struct dpllsim_dev {
-- 
2.56.0


  parent reply	other threads:[~2026-11-12 13:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-12 13:03 [PATCH net-next v4 00/14] dpll: add a simulated DPLL device driver Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 01/14] dpll: dpllsim: Add " Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 02/14] selftests: dpll: add test library and device lifecycle tests Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 03/14] dpll: dpllsim: Add configurable pins Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 04/14] selftests: dpll: add pin enumeration and property tests Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 05/14] dpll: dpllsim: Add support to set input pin state Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 06/14] selftests: dpll: add pin state tests Petr Oros
2026-11-12 13:03 ` Petr Oros [this message]
2026-11-12 13:03 ` [PATCH net-next v4 08/14] selftests: dpll: add pin priority test Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 09/14] dpll: dpllsim: Add support to set frequency on pins Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 10/14] selftests: dpll: add pin frequency test Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 11/14] dpll: dpllsim: Add support to adjust phase Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 12/14] selftests: dpll: add pin phase adjust test Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 13/14] selftests: dpll: add concurrency stress tests Petr Oros
2026-11-12 13:03 ` [PATCH net-next v4 14/14] selftests: dpll: add reference leak tests Petr Oros

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