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Thu, 12 Nov 2026 05:22:40 -0800 (PST) Received: from localhost.localdomain ([2a13:e746:396c:c600::31a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c504a3a621csm344076866b.12.2026.11.12.05.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 05:22:40 -0800 (PST) From: "Kordian Chmielewski (mlody1212)" To: netdev@vger.kernel.org Cc: Florian Fainelli , Jonas Gorski , Doug Berger , Andrew Lunn , Heiner Kallweit , Russell King , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , bcm-kernel-feedback-list@broadcom.com Subject: Re: BCM4908 Ethernet and 2.5G WAN: upstreaming plan and two questions Date: Thu, 12 Nov 2026 14:22:29 +0100 Message-ID: <20261112132229.340114-1-kudzo51@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261109231739.2561930-1-kudzo51@gmail.com> References: <20261109231739.2561930-1-kudzo51@gmail.com> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Three corrections to my mail above and my later correction. The AX11000 has three BCM43684 radios, not two; I mixed it up with the AX6000. I should not have written that the SoC SerDes gives the BCM54991E a 50 MHz clock. I took the 50 MHz from a comment in Broadcom's SerDes setup code, read it as the PHY's clock and did not test it. I have tested it now: with the SerDes held in IDDQ, PWRDWN and RESETPLL, the PHY answers MDIO right after its enable GPIO goes high, takes its firmware over MDIO and starts its CPU, and a running PHY keeps its link. So MDIO needs the enable GPIO, not the SerDes. The SerDes status still showed PLL lock, so I can't say the PLL itself stopped. And, unlike what I wrote in my earlier correction, the BCM54991E does not set MDIO_READ_FAIL on good Clause 45 reads: with a counter on the bit, 11640 reads, none with it set. My note was older than the fix that made the PHY answer at all. Kordian