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Sat, 14 Nov 2026 05:36:45 -0800 (PST) Received: from lake ([2a02:810d:d09:1b65:1a41:5e41:61a6:f0b6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49d69c21a17sm6657866f8f.50.2026.11.14.05.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2026 05:36:45 -0800 (PST) From: Christian Schmidbauer To: netdev@vger.kernel.org Cc: maxime.chevallier@bootlin.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, Oleksij Rempel , Christian Schmidbauer , stable@vger.kernel.org, Maxime Coquelin , Alexandre Torgue , Aaro Koskinen , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net v3 2/3] net: stmmac: dwmac1000: don't discard frames with only a checksum error Date: Sat, 14 Nov 2026 14:36:38 +0100 Message-ID: <20261114133640.3285413-3-opensource@grische.xyz> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20261114133640.3285413-1-opensource@grische.xyz> References: <20261114133640.3285413-1-opensource@grische.xyz> X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On dwmac1000 with enhanced descriptors, the hardware sets the Error Summary (ES) bit of the Rx descriptor not only for L2 errors but also for an L3/L4 checksum error. enh_desc_get_rx_status() returns discard_frame whenever ES is set, and since commit 1b746ce8b397 ("net: stmmac: don't overwrite discard_frame status") the checksum status is only evaluated for good frames. Return discard_frame only when ES comes with one of the L2 error bits. A frame with only a checksum error is then reported as csum_none and reaches the stack as CHECKSUM_NONE, so the stack verifies the checksum itself. This matches dwmac4, whose Error Summary bit does not cover checksum errors. RDES0 bit 7 is not in the mask, because depending on the core and on Rx checksum offload it reports a timestamp, an IP header checksum error or a giant frame, and enh_desc_get_rx_status() cannot tell which. In threshold Rx mode, a giant frame that fits one buffer therefore reaches the stack with a verified FCS. Also remove the pr_err that enh_desc_get_rx_status() prints when bit 7 is set. Once the MAC stops dropping checksum-error frames, any host on the link can flood the kernel log by sending frames with a bad IPv4 header checksum. This prepares for setting DMA_CONTROL_DT, which makes the MAC deliver checksum-error frames instead of dropping them in its Rx FIFO. Fixes: 1b746ce8b397 ("net: stmmac: don't overwrite discard_frame status") Cc: # 6.6.x: ee0aace5f844: net: stmmac: Correctly handle Rx checksum offload errors Cc: # 6.6.x Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Christian Schmidbauer --- v2: - Drop RDES0_LENGTH_ERROR from the mask of Error Summary bits. The length check further down already discards such a frame. - Explain in the commit message why RDES0 bit 7 is not treated as an L2 error. v1: https://lore.kernel.org/netdev/20261020190319.884375-1-opensource@grische.xyz/ drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c index 7ece8d4157a8..d0622f2605aa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c +++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c @@ -216,9 +216,6 @@ static int enh_desc_get_rx_status(struct stmmac_extra_stats *x, if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR)) x->rx_gmac_overflow++; - if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR)) - pr_err("\tIPC Csum Error/Giant frame\n"); - if (unlikely(rdes0 & RDES0_COLLISION)) x->rx_collision++; if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG)) @@ -230,7 +227,10 @@ static int enh_desc_get_rx_status(struct stmmac_extra_stats *x, if (unlikely(rdes0 & RDES0_CRC_ERROR)) { x->rx_crc_errors++; } - ret = discard_frame; + if (rdes0 & (RDES0_DESCRIPTOR_ERROR | RDES0_OVERFLOW_ERROR | + RDES0_COLLISION | RDES0_RECEIVE_WATCHDOG | + RDES0_MII_ERROR | RDES0_CRC_ERROR)) + ret = discard_frame; } /* After a payload csum error, the ES bit is set. -- 2.54.0