From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07EAF262A6 for ; Wed, 4 Feb 2026 22:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770242643; cv=none; b=nqFQtNzC08IXIdKWK/+9BFcba937V3QjQBAf3oDNlV3Csp+B2G2rYw/9Sd0aIZ6z8ecl/UgfBABPhblgOXGJEj0x57TGTcn6mVcMCoNXbbEVf22b/wpMKZOqFoBHeufpQCxGLSXWG9GUqKkVbKb6Hj3pv/iQTJsKC4t4jl1vS+o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770242643; c=relaxed/simple; bh=jDFqO+g2OcpArkcwt6C1iHwflk+ZmD+tFdd5a1y0Tn4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MWxxfsMsPsqleOCJBVqNPxnr3eIEZwPOpP/5G3xkGH3doCu0k1AQNOD++N604XtK6EK74ux5czMZlniTKHI8PH7mO5hL7S73Gftgl3tIjEvxYUPHmGY6iZwUf889m68fYgOgQWBksBveaxfpyZ1KAo27jDyM0x4YbpUp9e27QL8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=QX8FJnsw; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="QX8FJnsw" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=sjPwyNGA9xy8POgiuW0Tq0QzH0cSNVPVKMgCL48PxsA=; b=QX8FJnswsoHYefLJ2uxQ9cSJdv Ct7M/Ce3CQEZOx/pMyy8ZhYfHLFD5QUUNGFRvi3xXcRIFiN1o8D0V1cOhCKgfc31bzbLOxMRiM0cv rNEgb3KmbBBE+QrZtzh6+pVAoW5d43BCoKPCc+dni1OQfT7Kd+/jro0rbIt8ZNSvrebbDjIyVVX6y Q9MpyLZo95PnPlSFE3bePul4W5Uo+DZ0v+3AQqyIXgkGYpclY4FgxQBEMkhQOj5hjQ/Gi7NvaKneT FKh93TtRfz00xQZY6kCekx9qcI3QW/pyqyCtMRvNX3jtbc+5AC5+LPgtv7LGGYj9B+M0Ouq+2Nu47 pTQ5b9FQ==; Received: from i53875ac7.versanet.de ([83.135.90.199] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vnkyV-0071Wm-Sl; Wed, 04 Feb 2026 23:03:52 +0100 From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Andrew Lunn , "Russell King (Oracle)" Cc: Alexandre Torgue , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org, Paolo Abeni Subject: Re: [PATCH net-next 5/6] net: stmmac: rk: use rk_encode_wm16() for clock selection Date: Wed, 04 Feb 2026 23:03:51 +0100 Message-ID: <20297648.sWSEgdgrri@diego> In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Mittwoch, 4. Februar 2026, 10:14:38 Mitteleurop=C3=A4ische Normalzeit sc= hrieb Russell King (Oracle): > Use rk_encode_wm16() for RMII clock gating control, and also for the > io_clksel bit used to select the transmit clock between CRU-derived > and IO-derived clock sources. >=20 > Both of these were configured via the "set_clock_selection" method in > the SoC specific operations, but there is no requirement to change the > io_clksel except when enabling clocks. >=20 > It is also possible that we don't need to ungate the RMII clock if we > are operating in RGMII mode, but this commit makes no change there. >=20 > Split up the configuration of these as separate functions, and remove > the set_clock_selection() method. Since these clocking bits are in the > same register that we call the "speed" register, move the logic for > writing that register into rk_write_speed_grf_reg(). >=20 > Signed-off-by: Russell King (Oracle) > --- > .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 174 ++++++++---------- > 1 file changed, 75 insertions(+), 99 deletions(-) >=20 > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net= /ethernet/stmicro/stmmac/dwmac-rk.c > index 4099cbc5d0de..ed9adac70f0a 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > @@ -27,8 +27,17 @@ > struct rk_priv_data; > =20 > struct rk_clock_fields { > + /* io_clksel_cru_mask - io_clksel bit in clock GRF register which, > + * when set, selects the tx clock from CRU. > + */ > + u16 io_clksel_cru_mask; > + /* io_clksel_io_mask - io_clksel bit in clock GRF register which, > + * when set, selects the tx clock from IO. > + */ nit: comment stile does not seem to follow the kernel coding style https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Doc= umentation/process/coding-style.rst#n622 > + u16 io_clksel_io_mask; > u16 gmii_clk_sel_mask; > u16 rmii_clk_sel_mask; > + u16 rmii_gate_en_mask; > u16 mac_speed_mask; > }; [...] > + /* The io_clksel configuration can be either: > + * 0=3DCRU, 1=3DIO (rk3506, rk3520, rk3576) or > + * 0=3DIO, 1=3DCRU (rk3588) > + * where CRU means the transmit clock comes from the CRU and IO > + * means the transmit clock comes from IO. > + * > + * Handle this by having two masks. > + */ nit: same as above Other than these 2 nits, this looks good to me. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner #px30,rk3328,rk3568,rk3588