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[79.208.145.231]) by smtp.gmail.com with ESMTPSA id g1sm5764139wmc.25.2019.03.21.15.24.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 15:24:14 -0700 (PDT) Received: from localhost.daheim ([127.0.0.1] helo=debian64.localnet) by debian64.daheim with esmtp (Exim 4.92) (envelope-from ) id 1h766f-0007f6-Lk; Thu, 21 Mar 2019 23:24:13 +0100 From: Christian Lamparter To: Marek Behun Cc: Florian Fainelli , netdev@vger.kernel.org, Andrew Lunn , Michal =?utf-8?B?Vm9rw6HEjQ==?= , John Crispin , Wei Yongjun Subject: Re: [PATCH net-next 1/1] net: dsa: qca8k: Fix internal PHY MDIO address Date: Thu, 21 Mar 2019 23:24:13 +0100 Message-ID: <2275278.j5OWp99DLc@debian64> In-Reply-To: <20190321205555.358eaaee@nic.cz> References: <20190321182319.10664-1-marek.behun@nic.cz> <4f2160f2-28f1-bd61-86ee-3db77fd67ba4@gmail.com> <20190321205555.358eaaee@nic.cz> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org (Bottom post?) On Thursday, March 21, 2019 8:55:55 PM CET Marek Behun wrote: > Hi, > > Oh, I didn't know about Christian's patch. > > I shall test on our device tomorrow. If it works, we will use internal > PHY access. > > But I think that qca8k_port_to_phy should be used in the external mode > as well. On our device the PHYs are mapped on 0-4 on the master bus even > in that mode. Hm, it's not really a "external mode". But let's try one more time. The idea is that if an external mdio-bus (from the SoC) has already registered the PHY 0x0 - 0x4 from the QCA8337, the qca8k should not expose the same PHYs as it's own mdio-bus because then the PHYs end up being registered twice. If you look at the mdio-bus communications during boot you can definitly see the funkyness: every PHY gets initialized twice. You can also see this "duplication" in /sys/class/mdio_bus. In this directory you'll have a mdio-bus from the SoC and another one dsa-0:0 from the qca8k. If you look into those you'll notice that their both the same. As for why this happend. I think I found the culprit in a "missed" requirement from one of Andrew Lunn's reponses to the initial qca8k patch: In this post, he described the Device-Tree dts configuration we use today. But at the end he requests: "and remove the phy_read() and phy_write() functions." But from what I can tell, this important bit of information was lost during the night. Because they show up in v2+: https://lore.kernel.org/patchwork/patch/716989/ (So I guess I have to add Fixes: to my patch as well) Cheers, Christian