From: Jon Hunter <jonathanh@nvidia.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Revanth Kumar Uppala <ruppala@nvidia.com>,
"andrew@lunn.ch" <andrew@lunn.ch>,
"hkallweit1@gmail.com" <hkallweit1@gmail.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH 3/4] net: phy: aquantia: Poll for TX ready at PHY system side
Date: Tue, 30 Jul 2024 11:02:07 +0100 [thread overview]
Message-ID: <22cd777b-ffda-439b-b2e5-866235aba05e@nvidia.com> (raw)
In-Reply-To: <Zqi1O88vXK3Uonr1@shell.armlinux.org.uk>
On 30/07/2024 10:41, Russell King (Oracle) wrote:
> On Tue, Jul 30, 2024 at 10:36:12AM +0100, Jon Hunter wrote:
>>
>> On 29/07/2024 11:47, Russell King (Oracle) wrote:
>>
>> ...
>>
>>>> Apologies for not following up before on this and now that is has been a
>>>> year I am not sure if it is even appropriate to dig this up as opposed to
>>>> starting a new thread completely.
>>>>
>>>> However, I want to resume this conversation because we have found that this
>>>> change does resolve a long-standing issue where we occasionally see our
>>>> ethernet controller fail to get an IP address.
>>>>
>>>> I understand that your objection to the above change is that (per Revanth's
>>>> feedback) this change assumes interface has the link. However, looking at
>>>> the aqr107_read_status() function where this change is made the function has
>>>> the following ...
>>>>
>>>> static int aqr107_read_status(struct phy_device *phydev)
>>>> {
>>>> int val, ret;
>>>>
>>>> ret = aqr_read_status(phydev);
>>>> if (ret)
>>>> return ret;
>>>>
>>>> if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
>>>> return 0;
>>>>
>>>>
>>>> So my understanding is that if we don't have the link, then the above test
>>>> will return before we attempt to poll the TX ready status. If that is the
>>>> case, then would the change being proposed be OK?
>>>
>>> Here, phydev->link will be the _media_ side link. This is fine - if the
>>> media link is down, there's no point doing anything further. However,
>>> if the link is up, then we need the PHY to update phydev->interface
>>> _and_ report that the link was up (phydev->link is true).
>>>
>>> When that happens, the layers above (e.g. phylib, phylink, MAC driver)
>>> then know that the _media_ side interface has come up, and they also
>>> know the parameters that were negotiated. They also know what interface
>>> mode the PHY is wanting to use.
>>>
>>> At that point, the MAC driver can then reconfigure its PHY facing
>>> interface according to what the PHY is using. Until that point, there
>>> is a very real chance that the PHY <--> MAC connection will remain
>>> _down_.
>>>
>>> The patch adds up to a _two_ _second_ wait for the PHY <--> MAC
>>> connection to come up before aqr107_read_status() will return. This
>>> is total nonsense - because waiting here means that the MAC won't
>>> get the notification of which interface mode the PHY is expecting
>>> to use, therefore the MAC won't configure its PHY facing hardware
>>> for that interface mode, and therefore the PHY <--> MAC connection
>>> will _not_ _come_ _up_.
>>>
>>> You can not wait for the PHY <--> MAC connection to come up in the
>>> phylib read_status method. Ever.
>>>
>>> This is non-negotiable because it is just totally wrong to do this
>>> and leads to pointless two second delays.
>>
>>
>> Thanks for the feedback! We will go away, review this and see if we can
>> figure out a good/correct way to resolve our ethernet issue.
>
> Which ethernet driver is having a problem?
>
It is the drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c driver. It
works most of the time, but on occasion it fails to get a valid IP
address.
Thanks
Jon
--
nvpublic
next prev parent reply other threads:[~2024-07-30 10:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230628124326.55732-1-ruppala@nvidia.com>
2023-06-28 13:30 ` [PATCH 1/4] net: phy: aquantia: Enable Tx/Rx pause frame support in aquantia PHY Russell King (Oracle)
[not found] ` <ce4c10b5-c2cf-489d-b096-19b5bcd8c49e@lunn.ch>
2023-07-24 11:29 ` Revanth Kumar Uppala
2023-07-24 11:47 ` Russell King (Oracle)
[not found] ` <20230628124326.55732-3-ruppala@nvidia.com>
2023-06-28 13:33 ` [PATCH 3/4] net: phy: aquantia: Poll for TX ready at PHY system side Russell King (Oracle)
2023-07-24 11:29 ` Revanth Kumar Uppala
2023-07-24 11:57 ` Russell King (Oracle)
2024-07-19 13:27 ` Jon Hunter
2024-07-29 10:47 ` Russell King (Oracle)
2024-07-30 9:36 ` Jon Hunter
2024-07-30 9:41 ` Russell King (Oracle)
2024-07-30 10:02 ` Jon Hunter [this message]
2024-07-30 11:12 ` Russell King (Oracle)
2024-07-30 12:25 ` Jon Hunter
2024-09-24 10:33 ` Jon Hunter
[not found] ` <20230628124326.55732-4-ruppala@nvidia.com>
2023-06-28 13:43 ` [PATCH 4/4] net: phy: aqr113c: Enable Wake-on-LAN (WOL) Russell King (Oracle)
2023-07-24 11:29 ` Revanth Kumar Uppala
2023-07-24 12:29 ` Russell King (Oracle)
[not found] ` <c1aedb1e-e750-40ce-a19a-dfb21e2a971f@lunn.ch>
2023-07-24 11:30 ` Revanth Kumar Uppala
2023-06-28 13:46 ` [PATCH 1/4] net: phy: aquantia: Enable Tx/Rx pause frame support in aquantia PHY Russell King (Oracle)
[not found] ` <20230628124326.55732-2-ruppala@nvidia.com>
[not found] ` <57493101-413c-4f68-a064-f25e75fc2783@lunn.ch>
2023-07-24 11:29 ` [PATCH 2/4] net: phy: aquantia: Enable MAC Controlled EEE Revanth Kumar Uppala
2023-07-24 11:52 ` Russell King (Oracle)
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