* powerpc: net: gianfar ethernet broken on linux-3.10.29?
[not found] <2067855247.249513.1395772774452.JavaMail.root@mail>
@ 2014-03-25 19:26 ` Émeric Vigier
2014-03-26 13:02 ` Claudiu Manoil
0 siblings, 1 reply; 3+ messages in thread
From: Émeric Vigier @ 2014-03-25 19:26 UTC (permalink / raw)
To: netdev
[-- Attachment #1: Type: text/plain, Size: 2659 bytes --]
Hi guys,
I work on a Freescale MPC8347 custom board. I ported u-boot-v2014.01 on it. My config is attached.
I ported linux-3.2.52 (long-term). DTS is attached.
linux-3.2.52 being a bit old, I switched to linux-3.10.29 (long-term).
For linux-3.10.29, I use the same DTS.
linux-3.2.52
------------
Ethernet works on both u-boot and linux-3.2.52: i.e. I can ping, and use a rootfs over NFS.
I attached outputs from u-boot, ifconfig, mii-diag and ethtool utilities (mii-ethtool-ifconfig-3.2.52.txt).
linux-3.10.29
-------------
Ethernet is broken: i.e. I can up the link, it says 100/Full-duplex, but I cannot ping anybody.
When I ping the device from my PC, I get "RX interrupts" (eth0_g0_rx) but no "RX bytes".
Because I cannot use NFS, I mounted rootfs from a compressed initramfs.
I attached outputs from u-boot, ifconfig, mii-diag and ethtool utilities (mii-ethtool-ifconfig-3.10.29.txt).
mii-diag dumps the PHY registers. Only one register differs between the two kernels: 0x15
Datasheet says this register is reserved. I have no control over it.
After a week long of trials, I believe the PHY is fine. Problem might come from the gianfar driver.
Which has widely changed between 3.2 and 3.10: 51 patches.
$ git log --oneline v3.2.52..v3.10.29 drivers/net/ethernet/freescale/gianfar.c | wc -l
51
I have not "git bisect" the bug, fearing that I would struggle to build the resulting kernel due to
changes in net/ and the driver model.
Hardware
--------
The architecture is as follows:
+----------------------+
| MPC8347 +----------+
| | gianfar |
| | ethernet |
| | TSEC0 |
| | |
| | +------+ +-------------+
| | | MDIO | <--> | BCM5241 PHY |
| | | MII | | addr:0 |
| | +------+ +-------------+
| +----------+
+----------------------+
MDIO is connected in MII: 4 TX, 4RX, COL, CRS, TXCLK, RXCLK, MDIO, MDC.
Auto-negotiation is disabled by hardware (pull-ups), speed is fixed to 100Mbps and full-duplex.
The PHY lies at address 0.
MDIO link is fine: I can read/write registers on the PHY.
I made several trials, list is not exhaustive:
- switch to Generic PHY driver
- switch to Broadcom BCM5241 PHY driver
- fixed-link = <0 1 100 0 0> in DTS
- stub tbi-phy node in DTS
- stub ethernet1 node (TSEC1) in DTS
- reset the PHY with mii-diag
- remove the interrupt attribute in DTS
I made it work on linux-3.10.29 once, only 3/4 min after bootup. But I couldn't catch why...
Do you guys see what could be wrong in my config?
Or what has changed in linux-3.{4,6,8,10} that could break my ethernet?
thanks,
Emeric
[-- Attachment #2: mii-ethtool-ifconfig-3.2.52.txt --]
[-- Type: text/plain, Size: 4289 bytes --]
U-Boot 2014.01 (Mar 12 2014 - 14:00:10)MPC83XX
Reset Status:
CPU: e300c1, MPC8347_TBGA_EA, Rev: 3.0 at 533.333 MHz, CSB: 266.667 MHz
Board: Freescale MPC8347EA-NVR Alstom
...
tsec_get_interface: ecntrl(0xe0024020): 0x0
init_phy: interface: 0
TSEC0 connected to Broadcom BCM5241
MPC8347AE-NVR> print ipaddr
ipaddr=10.130.2.115
MPC8347AE-NVR> print netmask
netmask=255.255.254.0
MPC8347AE-NVR> ping $serverip
Trying TSEC0
Speed: 100, full duplex
Using TSEC0 device
host 10.130.2.119 is alive
MPC8347AE-NVR> run nfsboot
...
[ 0.562434] Fixed MDIO Bus: probed
[ 0.566343] Freescale PowerQUICC MII Bus: probed
[ 0.573589] fsl-gianfar e0024000.ethernet: eth0: mac: 08:00:3e:03:01:11
[ 0.580260] fsl-gianfar e0024000.ethernet: eth0: Running with NAPI enabled
[ 0.587163] fsl-gianfar e0024000.ethernet: eth0: RX BD ring size for Q[0]: 256
[ 0.594412] fsl-gianfar e0024000.ethernet: eth0: TX BD ring size for Q[0]: 256
...
[ 13.113263] Trying 100/FULL
[ 14.113090] PHY: mdio@e0024520:00 - Link is Up - 100/Full
[ 14.133327] IP-Config: Gateway not on directly connected network.
[ 14.139811] md: Skipping autodetection of RAID arrays. (raid=autodetect will force)
[ 14.154938] VFS: Mounted root (nfs filesystem) on device 0:13.
[ 14.161169] devtmpfs: mounted
[ 14.165414] Freeing unused kernel memory: 164k freed
...
# uname -a
Linux mpc8347-NVR 3.2.52 #1 Fri Mar 7 16:23:02 EST 2014 ppc GNU/Linux
# ifconfig eth0
eth0 Link encap:Ethernet HWaddr 08:00:3E:03:01:11
inet addr:10.130.2.115 Bcast:10.130.3.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:2519 errors:0 dropped:0 overruns:0 frame:175
TX packets:1175 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:3072045 (2.9 MiB) TX bytes:185626 (181.2 KiB)
Base address:0x6000
# ping 10.130.2.119
PING 10.130.2.119 (10.130.2.119): 56 data bytes
64 bytes from 10.130.2.119: seq=0 ttl=64 time=0.717 ms
# mii-diag -v eth0
mii-diag.c:v2.11 3/21/2005 Donald Becker (becker@scyld.com)
http://www.scyld.com/diag/index.html
Using the new SIOCGMIIPHY value on PHY 0 (BMCR 0x2100).
Basic mode control register 0x2100: Auto-negotiation disabled, with
Speed fixed at 100 mbps, full-duplex.
You have link beat, and everything is working OK.
This transceiver is capable of 100baseTx-FD 100baseTx 10baseT-FD 10baseT.
Able to perform Auto-negotiation, negotiation not complete.
Link partner information is not exchanged when in fixed speed mode.
End of basic transceiver information.
libmii.c:v2.11 2/28/2005 Donald Becker (becker@scyld.com)
http://www.scyld.com/diag/index.html
MII PHY #0 transceiver registers:
2100 780d 0143 bc31 01e1 0000 0004 2001
0000 0000 0000 0000 0000 0000 0000 0000
d000 0301 0000 0000 0200 029d 0100 0000
0037 000d bf00 008e 0027 c000 0000 000b.
Basic mode control register 0x2100: Auto-negotiation disabled!
Speed fixed at 100 mbps, full-duplex.
Basic mode status register 0x780d ... 780d.
Link status: established.
Capable of 100baseTx-FD 100baseTx 10baseT-FD 10baseT.
Able to perform Auto-negotiation, negotiation not complete.
Vendor ID is 00:50:ef:--:--:--, model 3 rev. 1.
No specific information is known about this transceiver type.
I'm advertising 01e1: 100baseTx-FD 100baseTx 10baseT-FD 10baseT
Advertising no additional info pages.
IEEE 802.3 CSMA/CD protocol.
Link partner capability is 0000:.
Negotiation did not complete.
# ethtool eth0
Settings for eth0:
Supported ports: [ MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Supported pause frame use: No
Supports auto-negotiation: Yes
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Advertised pause frame use: No
Advertised auto-negotiation: Yes
Speed: 100Mb/s
Duplex: Full
Port: MII
PHYAD: 0
Transceiver: external
Auto-negotiation: off
Current message level: 0x0000003f (63)
drv probe link timer ifdown ifup
Link detected: yes
[-- Attachment #3: mii-ethtool-ifconfig-3.10.29.txt --]
[-- Type: text/plain, Size: 4996 bytes --]
U-Boot 2014.01 (Mar 12 2014 - 14:00:10)MPC83XX
Reset Status: Software Hard, External/Internal Soft, External/Internal Hard
CPU: e300c1, MPC8347_TBGA_EA, Rev: 3.0 at 533.333 MHz, CSB: 266.667 MHz
Board: Freescale MPC8347EA-NVR Alstom
...
tsec_get_interface: ecntrl(0xe0024020): 0x0
init_phy: interface: 0
TSEC0 connected to Broadcom BCM5241
MPC8347AE-NVR> setenv ramdiskaddr -
Initial value for argc=3
Final value for argc=3
MPC8347AE-NVR> setenv bootfile uImage-3.10.29-ramfs-gz
Initial value for argc=3
Final value for argc=3
MPC8347AE-NVR> run ramboot
...
[ 1.270385] libphy: Fixed MDIO Bus: probed
[ 1.274992] libphy: Freescale PowerQUICC MII Bus: probed
[ 1.291791] fsl-gianfar e0024000.ethernet eth0: mac: 08:00:3e:03:01:11
[ 1.298386] fsl-gianfar e0024000.ethernet eth0: Running with NAPI enabled
[ 1.305202] fsl-gianfar e0024000.ethernet eth0: RX BD ring size for Q[0]: 256
[ 1.312359] fsl-gianfar e0024000.ethernet eth0: TX BD ring size for Q[0]: 256
...
# uname -a
Linux mpc8347-NVR 3.10.29 #4 Thu Mar 13 13:45:50 EDT 2014 ppc GNU/Linux
# ifconfig eth0 10.130.2.115 netmask 255.255.254.0
[ 129.189008] gianfar_driver: adjust_link: spd:100 dupl:1 link:1 intf:2 autoneg:0 dev_flags:0 state:6
[ 129.198081] libphy: mdio@e0024520:00 - Link is Up - 100/Full
# ifconfig eth0
eth0 Link encap:Ethernet HWaddr 08:00:3E:03:01:11
inet addr:10.130.2.115 Bcast:10.130.3.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:3 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:126 (126.0 B)
Base address:0x2000
# ping 10.130.2.119
PING 10.130.2.119 (10.130.2.119): 56 data bytes
# ifconfig eth0
eth0 Link encap:Ethernet HWaddr 08:00:3E:03:01:11
inet addr:10.130.2.115 Bcast:10.130.3.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:6 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:252 (252.0 B)
Base address:0x2000
# cat /proc/interrupts
CPU0
16: 517 IPIC Level serial
18: 32 IPIC Level i2c-mpc
19: 82 IPIC Level i2c-mpc
20: 0 IPIC Level fsl_spi
22: 0 IPIC Level sata_sil
32: 12 IPIC Level eth0_g0_tx
33: 24 IPIC Level eth0_g0_rx
34: 0 IPIC Level eth0_g0_er
77: 0 IPIC Level fsl-lbc
LOC: 48686 Local timer interrupts
SPU: 0 Spurious interrupts
CNT: 0 Performance monitoring interrupts
MCE: 0 Machine check exceptions
#
# ethtool eth0
Settings for eth0:
Supported ports: [ MII ]
Supported link modes: 100baseT/Full
Supported pause frame use: No
Supports auto-negotiation: No
Advertised link modes: 100baseT/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Speed: 100Mb/s
Duplex: Full
Port: MII
PHYAD: 0
Transceiver: external
Auto-negotiation: off
Current message level: 0x0000003f (63)
drv probe link timer ifdown ifup
Link detected: yes
# mii-diag -v eth0
mii-diag.c:v2.11 3/21/2005 Donald Becker (becker@scyld.com)
http://www.scyld.com/diag/index.html
Using the new SIOCGMIIPHY value on PHY 0 (BMCR 0x2100).
Basic mode control register 0x2100: Auto-negotiation disabled, with
Speed fixed at 100 mbps, full-duplex.
You have link beat, and everything is working OK.
This transceiver is capable of 100baseTx-FD 100baseTx 10baseT-FD 10baseT.
Able to perform Auto-negotiation, negotiation not complete.
Link partner information is not exchanged when in fixed speed mode.
End of basic transceiver information.
libmii.c:v2.11 2/28/2005 Donald Becker (becker@scyld.com)
http://www.scyld.com/diag/index.html
MII PHY #0 transceiver registers:
2100 780d 0143 bc31 01e1 0000 0004 2001
0000 0000 0000 0000 0000 0000 0000 0000
d000 0301 0000 0000 0200 0000 0100 0000
0037 000d bf00 008e 0027 c000 0000 000b.
Basic mode control register 0x2100: Auto-negotiation disabled!
Speed fixed at 100 mbps, full-duplex.
Basic mode status register 0x780d ... 780d.
Link status: established.
Capable of 100baseTx-FD 100baseTx 10baseT-FD 10baseT.
Able to perform Auto-negotiation, negotiation not complete.
Vendor ID is 00:50:ef:--:--:--, model 3 rev. 1.
No specific information is known about this transceiver type.
I'm advertising 01e1: 100baseTx-FD 100baseTx 10baseT-FD 10baseT
Advertising no additional info pages.
IEEE 802.3 CSMA/CD protocol.
Link partner capability is 0000:.
Negotiation did not complete.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #4: mpc8347nvr.dts --]
[-- Type: text/x-csrc; name=mpc8347nvr.dts, Size: 8788 bytes --]
/*
* MPC8347-NVR Device Tree Source
*
* Copyright 2014 Alstom Transport Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8347NVR";
compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8347@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc8347@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>; // from bootloader
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
gpio1: gpio-controller@c00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupts = <74 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency=<87000>;
dfsrr;
eeprom1: at24@50 {
compatible = "at24,24c256";
reg = <0x50>;
};
lm75@4c {
compatible = "national,lm75";
reg = <0x4c>;
};
rtc@68 {
compatible = "stm,m41t65";
reg = <0x68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <15 0x8>;
interrupt-parent = <&ipic>;
clock-frequency=<66000>;
dfsrr;
pca9541@70 {
compatible = "philips,pca9541";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
pcf8574: gpio@24 {
#gpio-cells = <2>;
compatible = "ti,pcf8574";
reg = <0x24>;
gpio-controller;
lines-initial-states = <0x00>;
};
lm75@4c {
compatible = "national,lm75";
reg = <0x4c>;
};
eeprom2: at24@54 {
compatible = "st-micro,24c04";
reg = <0x54>;
};
};
};
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
linux,network-index = <0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
/* BCM5241 */
phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x0>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
interrupt-parent = <&ipic>;
/* Vitesse 7385 isn't on the MDIO bus */
fixed-link = <1 1 1000 0 0>;
linux,network-index = <1>;
tbi-handle = <&tbi1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>; // from bootloader
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
current-speed = <115200>;
status = "okay";
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>; // from bootloader
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
current-speed = <115200>;
status = "okay";
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
device_type = "ipic";
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x10 - SATA */
0x8000 0x0 0x0 0x1 &ipic 18 0x8 /* SATA_INTA */
>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
localbus@e0005000 {
#address-cells = <2>; /* <CS offset> */
#size-cells = <1>; /* within 32bits boundaries */
compatible = "fsl,mpc8349e-localbus",
"fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0x0 0x0 0xf8000000 0x08000000>; /* flash */
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
flash@0,0 {
compatible = "amd,s29gl512n", "cfi-flash";
reg = <0x0 0x0 0x08000000>; /* <CS offset size> */
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>; /* within 32bits boundaries */
/* partitions */
partition@0 {
label = "kernel";
reg = <0x00000000 0x000800000>;
};
partition@800000 {
label = "kernel-backup";
reg = <0x00800000 0x000800000>;
};
partition@1000000 {
label = "rootfs";
reg = <0x01000000 0x02000000>;
};
partition@3000000 {
label = "configuration";
reg = <0x03000000 0x01000000>;
};
partition@4000000 {
label = "rootfs-backup";
reg = <0x04000000 0x02000000>;
};
partition@6000000 {
label = "boot-backup";
reg = <0x06000000 0x00060000>;
};
partition@6100000 {
label = "environment-backup";
reg = <0x06100000 0x00020000>;
};
partition@6200000 {
label = "local-log";
reg = <0x06200000 0x00100000>;
};
partition@6800000 {
label = "configuration-backup";
reg = <0x06800000 0x01000000>;
};
partition@7f00000 {
label = "boot";
reg = <0x07f00000 0x000060000>;
read-only;
};
partition@7f60000 {
label = "environment";
reg = <0x07f60000 0x000020000>;
read-only;
};
};
};
};
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #5: MPC8347NVR.h --]
[-- Type: text/x-chdr; name=MPC8347NVR.h, Size: 23229 bytes --]
/*
* Copyright (C) Alstom Transport, Inc. 2014.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
MPC8347EA-NVR board configuration file
Memory map:
0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
0xF001_0000-0xF001_FFFF Local bus expansion slot
0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
I2C address list:
Align. Board
Bus Addr Part No. Description Length Location
----------------------------------------------------------------
I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
I2C1 0x20 PCF8574 I2C Expander 0 U8
I2C1 0x21 PCF8574 I2C Expander 0 U10
I2C1 0x38 PCF8574A I2C Expander 0 U8
I2C1 0x39 PCF8574A I2C Expander 0 U10
I2C1 0x51 (DDR) DDR EEPROM 1 U1
I2C1 0x68 DS1339 RTC 1 U68
Note that a given board has *either* a pair of 8574s or a pair of 8574As.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
#define CONFIG_SYS_LOWBOOT
#endif
/*
* High Level Configuration Options
*/
#define CONFIG_MPC83xx 1
#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
#define CONFIG_MPC8347NVR
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#endif
#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
#undef CONFIG_MISC_INIT_F /* runs vsc7385 and CF code, not needed */
#define CONFIG_MISC_INIT_R /* checks boot EEPROM content, needed */
/*
* On-board devices
*/
#ifdef CONFIG_MPC8347NVR
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH/* to get fat, ide commands */
#undef CONFIG_VSC7385_ENET /* !VSC7385 ethernet support */
#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
#undef CONFIG_SYS_USB_HOST /* !use the EHCI USB controller */
#endif
#define CONFIG_PCI
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C
#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
/*
* Device configurations
*/
/* I2C */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
#define CONFIG_SYS_RTC_BUS_NUM 0 /* The I2C bus for RTC */
#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
/* Don't probe these addresses: */
#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
{1, CONFIG_SYS_I2C_8574_ADDR2}, \
{1, CONFIG_SYS_I2C_8574A_ADDR1}, \
{1, CONFIG_SYS_I2C_8574A_ADDR2} }
/* Bit definitions for the 8574[A] I2C expander */
/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
#define I2C_8574_REVISION 0x03
#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
#endif
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
#undef CONFIG_IDE_RESET
#undef CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
#define CONFIG_SYS_ATA_REG_OFFSET 0
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
#define CONFIG_SYS_ATA_STRIDE 2
/* If a CF card is not inserted, time out quickly */
#define ATA_RESET_TIME 1
#endif
/*
* SATA
*/
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LIBATA
#define CONFIG_LBA48
#endif
#ifdef CONFIG_SYS_USB_HOST
/*
* Support USB
*/
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
/* Current USB implementation supports the only USB controller,
* so we have to choose between the MPH or the DR ones */
#if 1
#define CONFIG_HAS_FSL_MPH_USB
#else
#define CONFIG_HAS_FSL_DR_USB
#endif
#endif
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x2000
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
/* No SPD? Then manually set up DDR parameters */
#ifndef CONFIG_SPD_EEPROM
#define CONFIG_SYS_DDR_SIZE 256 /* Mb */
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_0 0x00110104
#define CONFIG_SYS_DDR_TIMING_1 0x4C43E441
#define CONFIG_SYS_DDR_TIMING_2 0x00004841 /* P9-45, may need tuning */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#endif
/*
*Flash on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* 127 64KB sectors + 8 8KB sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* The ITX has two flash chips, but the ITX-GP has only one. To support both
boards, we say we have two, but don't display a message if we find only one. */
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x4000000}
#define CONFIG_SYS_FLASH_SIZE 128 /* FLASH size in MB */
#undef CONFIG_SYS_FLASH_PROTECTION
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFEFFE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
/*
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
/* Flash */
/* BR0(0x5000) = 0xF8000000 | 0x1000 | 0x0 | 0x1 = 0xF8001001 */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 \
| BR_MS_GPCM \
| BR_V)
/* 0xF8000000 | 0x800 | 0x600 | 0x100 | 0xF0 | 0x1 = 0xF8000FF1 */
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
/* 0x80000000 | 0x1A = 0x8000001A */
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_SYS_VSC7385_BASE 0xF8000000
/* 0xF8000000 | 0x800 | 0x0 | 0x1 = 0xF8000801 */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
| BR_PS_8 \
| BR_MS_GPCM \
| BR_V)
/* 0xFFFE0000 | 0x800 | 0x100 | 0xF0 | 0x8 | 0x4 | 0x2 | 0x1 =
* 0xFFFE09FF */
#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
| OR_GPCM_CSNT \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_SETA \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
#define CONFIG_SYS_CF_BASE 0xF0000000
// 0xF0000000 | 0x1000 | 0x80 | 0x1 = 0xF0001081
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
| BR_PS_16 \
| BR_MS_UPMA \
| BR_V)
// 0xFFFF8000 | 0x100 = 0xFFFF8100
#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
/*
* U-Boot memory configuration
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
/* 0xFFF00000 > 0xF8000000 */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
* LCRR: DLL bypass, Clock divider is 2
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000
/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT 0x32000000
/* LB refresh timer prescal, 266MHz/32*/
#define CONFIG_SYS_LBC_MRTPR 0x20000000
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* PCI
*/
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_MPC83XX_PCI2
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512MB */
#define CONFIG_SYS_PCI1_MMIO_BASE \
(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x00000000 /* disabled */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16MB */
#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_PCI2_MEM_BASE \
(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512MB */
#define CONFIG_SYS_PCI2_MMIO_BASE \
(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS \
(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#endif
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR 0x00000000
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
#define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
#define CONFIG_PCI_66M
#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
#endif
/* TSEC */
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#undef CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
#define CONFIG_TSEC1
#define CONFIG_ETHADDR 08:00:3e:03:01:11
#define CONFIG_ETH1ADDR 08:00:3e:03:01:12
#define CONFIG_IPADDR 10.130.2.115
#define CONFIG_SERVERIP 10.130.2.119
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.254.0
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x00
#define TSEC1_PHYIDX 0
#define TSEC1_FLAGS TSEC_REDUCED /* RGMII, 100BaseT */
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
#define TSEC2_FLAGS TSEC_GIGABIT
#endif
#define CONFIG_ETHPRIME "Freescale TSEC"
#endif
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH
/* 0xFFF00000 + 0x60000 = 0xFFF60000 */
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for environment */
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
#undef CONFIG_FLASH_CFI_DRIVER
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
|| defined(CONFIG_USB_STORAGE)
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_SUPPORT_VFAT
#endif
#ifdef CONFIG_COMPACT_FLASH
#undef CONFIG_CMD_IDE
#endif
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_CMD_SATA
#endif
#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
#define CONFIG_CMD_EXT2
#endif
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_SYS_I2C
#define CONFIG_CMD_I2C
#endif
#ifdef CONFIG_TSEC_ENET
#define CONFIG_CMD_MII
#endif
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#define CONFIG_SYS_PROMPT "MPC8347AE-NVR> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
/* 0x0 | 0x0 | 0x04000000 | 0x0 | 0x40000 = 0x04040000 */
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_4X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CORE_TO_CSB_2X1)
#ifdef CONFIG_SYS_LOWBOOT
/* 0x80000000 | 0x0 | 0x20000000 | 0x10000000 | 0x0 | 0x0 | 0x0 | 0x0 |
* 0x00600000 | 0x8000 | 0x2000 = 0xB060A000 */
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
#else
/* 0x80000000 | 0x0 | 0x20000000 | 0x0 | 0x0 | 0x04000000 | 0x0 | 0x0 |
* 0x00600000 | 0x8000 | 0x2000 = 0xA460A000 */
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
#endif
/*
* System performance
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
//#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
//#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
/*
* System IO Config
*/
/* Needed for gigabit to work on TSEC 1 */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
/* no USB */
#define CONFIG_SYS_SICRL (SICRL_LDP_A)
#define CONFIG_SYS_HID0_INIT 0x00000000
#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#else
#define CONFIG_SYS_IBAT1L 0
#define CONFIG_SYS_IBAT1U 0
#define CONFIG_SYS_IBAT2L 0
#define CONFIG_SYS_IBAT2U 0
#endif
#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#else
#define CONFIG_SYS_IBAT3L 0
#define CONFIG_SYS_IBAT3U 0
#define CONFIG_SYS_IBAT4L 0
#define CONFIG_SYS_IBAT4U 0
#endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
| BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
| BATL_PP_RW \
| BATL_MEMCOHERENCE \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT7L 0
#define CONFIG_SYS_IBAT7U 0
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_NETDEV "eth0"
#define CONFIG_HOSTNAME "mpc8347nvr"
/* Default path and filenames */
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8347nvr.dtb"
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS \
"root=/dev/nfs rw" \
" nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
" ip=" __stringify(CONFIG_IPADDR) ":" \
__stringify(CONFIG_SERVERIP) ":" \
__stringify(CONFIG_GATEWAYIP) ":" \
__stringify(CONFIG_NETMASK) ":" \
CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
" console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=" __stringify(CONFIG_CONSOLE) "\0" \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
" console=$console,$baudrate $othbootargs; " \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw" \
" console=$console,$baudrate $othbootargs; " \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#endif
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