Re: [PATCH net-next v2 0/2] net: phy: Add Maxio MAE0621A support

[Andre Przywara <andre.przywara@arm.com>]

Hi,

thanks for sending this, one question and an update below ...

On 7/17/26 05:39, Liu Changjie wrote:
> Add a binding and PHY driver for the Maxio MAE0621A Gigabit Ethernet
> PHY. The driver matches the exact PHY ID and optionally selects a
> 125 MHz clock on CLKOUT. When the property is absent, the driver
> preserves the hardware strap or bootloader setting.
> 
> This was tested on the LCKFB Taishan Pi 3M. With the PHY's default
> CLKOUT configuration, the RK3576 GMAC negotiated a 1 Gbit/s link but
> the data path did not work. A read-modify-write of page 0xa43,
> register 0x19, setting bits 0 and 11 produced a readback value of
> 0x0823 and restored the data path without changing the RGMII delays.
> The readback also confirmed that the unrelated set bits were
> preserved.
> 
> Only the 125 MHz setting has been exercised on hardware and only that
> value is exposed by this series. The 0 and 25 MHz choices from the
> initial draft have been removed.

So what is this clock for, exactly? Is that the RXC clock, supposed to 
depend on the line speed? Then it would need to change if a 100MBit/s 
link is negotiated?
Or is this something else entirely, and merely used as an optional 
auxiliary clock, to support a switch or other network chips?

If I read the schematic of that Taishan board correctly, it's the 
former? But it's odd that both on the Radxa Cubie A5E (sporting the same 
-Q3C variant) and the X96QPro+ box (-Q2C) don't need any extra setting, 
and the clock there looks like the normal PHY controlled RXC clock.

> Public documentation for the MAE0621A register is not available. The

There seems to be now a datasheet, explaining all the non-standard 
registers, including the one for the 125MHz clock out register:

https://www.lcsc.com/datasheet/C49308069.pdf

If the link doesn't work (in the future), just find the PHY in the LCSC 
catalogue, it should have a link to the datasheet there.

Cheers,
Andre

> exact definitions of page 0xa43, register 0x19 bits 0 and 11, their
> reset defaults, and whether a soft reset is required after changing
> them still need confirmation from Maxio. The register programming in
> this series is therefore supported by the hardware A/B result, not by
> a public datasheet citation.
> 
> Hardware tests with the 125 MHz setting:
> - all supported 10/100/1000 Mbit/s link modes
> - 100 ICMP packets in each direction with no loss
> - 936/934 Mbit/s host-to-board iperf3, no retransmits
> - 943/941 Mbit/s board-to-host iperf3, no retransmits
> - link unplug/replug and a normal reboot, followed by another 100 ICMP
>    packets in each direction with no loss
> - no RX errors, missed packets, carrier errors or collisions
> 
> Static tests on net-next commit f6f3b36c15ed:
> - dt_binding_check with dtschema 2026.6
> - W=1 arm64 defconfig build of drivers/net/phy/maxio.o with GCC 10.3
> - W=1 arm64 allmodconfig build of drivers/net/phy/maxio.o with GCC 10.3
> - git diff --check and checkpatch.pl
> 
> Changes in v2:
> - Extend hardware validation to all supported 10/100/1000 Mbit/s link
>    modes.
> - Keep the binding limited to the tested 125 MHz setting. CLKOUT-disable
>    support can be added later after its register behavior is documented
>    and tested.
> - No binding or driver code changes.
> 
> Link: https://lore.kernel.org/r/MN0PR19MB6091CD5A84D2DA5DACF434DAACF92@MN0PR19MB6091.namprd19.prod.outlook.com [v1]
> 
> Liu Changjie (2):
>    dt-bindings: net: Add Maxio MAE0621A PHY
>    net: phy: Add support for the Maxio MAE0621A
> 
>   .../bindings/net/maxio,mae0621a.yaml          |  38 +++++++
>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>   drivers/net/phy/Kconfig                       |   8 ++
>   drivers/net/phy/Makefile                      |   1 +
>   drivers/net/phy/maxio.c                       | 103 ++++++++++++++++++
>   5 files changed, 152 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/net/maxio,mae0621a.yaml
>   create mode 100644 drivers/net/phy/maxio.c
> 
> 
> base-commit: f6f3b36c15ed44de1fbb44e645e4fae8c4a4453e