From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jose Abreu Subject: Re: STMMAC driver with TSO enabled issue Date: Mon, 28 May 2018 11:56:18 +0100 Message-ID: <2f6d4a0e-43cd-a67b-1f0a-5d358ac05c83@synopsys.com> References: <89c0a735-9e34-89c6-7692-579e48dadaa6@nvidia.com> <77c98a42-195f-b597-711d-8c2e8b55f266@synopsys.com> <5309d046-fc6f-bc63-06dc-6cc98276dce4@nvidia.com> <77ff3baf-fec5-f0a2-9fdf-caa63d4944d0@synopsys.com> <06ec3e2e-c41a-5f19-ffd8-51c5453d586b@synopsys.com> <3143ce1f-30e7-6b8d-06b5-6048abab54bc@nvidia.com> <78914761-0375-5929-ed88-5225e0e260b9@synopsys.com> <94cda7c4-127c-cae1-e51e-8853224065e2@nvidia.com> <957ba2dd-72e0-1f93-e291-eb8cf2145f8d@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: Bhadram Varka , Jose Abreu , "netdev@vger.kernel.org" , Joao Pinto Return-path: Received: from smtprelay.synopsys.com ([198.182.37.59]:50331 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1164507AbeE1K43 (ORCPT ); Mon, 28 May 2018 06:56:29 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id 45F7A1E133E for ; Mon, 28 May 2018 12:56:27 +0200 (CEST) In-Reply-To: <957ba2dd-72e0-1f93-e291-eb8cf2145f8d@nvidia.com> Sender: netdev-owner@vger.kernel.org List-ID: Hi Bhadram, On 28-05-2018 10:15, Bhadram Varka wrote: > Hi Jose, > > On 5/25/2018 8:02 PM, Jose Abreu wrote: >> On 25-05-2018 15:25, Bhadram Varka wrote: >>> Hi Jose, >>> >>> On 5/25/2018 7:35 PM, Jose Abreu wrote: >>>> Hi Bhadram, >>>> >>>> On 25-05-2018 05:41, Bhadram Varka wrote: >>>>> Hi Jose, >>>>> >>>>> On 5/24/2018 3:01 PM, Jose Abreu wrote: >>>>>> Hi Bhadram, >>>>>> >>>>>> On 24-05-2018 06:58, Bhadram Varka wrote: >>>>>>> >>>>>>> After some time if check Tx descriptor status - then I see >>>>>>> only >>>>>>> below >>>>>>> >>>>>>> [..] >>>>>>> [85788.286730] 027 [0x827951b0]: 0xf854f000 0x0 0x16d8 >>>>>>> 0x90000000 >>>>>>> >>>>>>> index 025 and 026 descriptors processed but not index 027. >>>>>>> >>>>>>> At this stage Tx DMA is always in below state - >>>>>>> >>>>>>> ■ 3'b011: Running (Reading Data from system memory >>>>>>> buffer and queuing it to the Tx buffer (Tx FIFO)) >>>>>> >>>>>> Thats strange, I think the descriptors look okay though. I >>>>>> will >>>>>> need the registers values (before the lock) and, if >>>>>> possible, the >>>>>> git bisect output. >>>>> >>>>> Attaching the register dump file after the issue observed. >>>>> Please check once. >>>>> >>>> >>>> ----->8----- >>>> 0x112c = 0x0000003F >>>> 0x11ac = 0x0000003F >>>> 0x122c = 0x0000003F >>>> 0x12ac = 0x0000003F >>>> >>>> 0x1130 = 0x0000003F >>>> 0x11b0 = 0x0000003F >>>> 0x1230 = 0x0000003F >>>> 0x12b0 = 0x0000003F >>>> ----->8----- >>>> >>>> This can't be right, it should be DMA_{RX/TX}_SIZE - 1 = >>>> 511. Did >>>> you change these values in the code? >>>> >>> >>> Yes. I have changed the descriptor length to 64 - so that >>> searching for the current descriptor status would be easy. >> >> Ok, it shouldn't impact anything. The only thing I'm remembering >> now is that you can have TSO not enabled in all DMA channels (HW >> configuration allows this). Please check if TSO in single-queue >> works. > TSO works fine if only single queue enabled. I don't see any > limitation from HW side because TSO works fine with other > driver which we received from Synopsys with IP drop. You need to check with HW team if TSO is enabled for all channels because you can have TSO channels < DMA channels and there is no way to confirm this in the registers. Also check if received driver is routing packets to queue != 0. Thanks and Best Regards, Jose Miguel Abreu > > > Thanks, > Bhadram.