Re: [PATCH v3 1/3] dt-bindings: clock: rockchip: Add RK3572 CRU

["Heiko Stübner" <heiko@sntech.de>]

Am Dienstag, 27. Oktober 2026, 11:17:08 Mitteleuropäische Normalzeit schrieb Krzysztof Kozlowski:
> On Mon, Oct 26, 2026 at 02:56:47PM +0800, Cunhao Lu wrote:
> > From: Elaine Zhang <zhangqing@rock-chips.com>
> > 
> > The RK3572 CRU uses the PMU0 GRF for the AUPLL reference mux.
> > Describe the controller and define its clock and reset IDs.
> > 
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > 
> > - Documented the xin24m input.
> > - Made the PMU0 GRF phandle required.
> > - Updated the example.
> > - Closed the reset ID gap while preserving each named reset's register
> >   mapping.
> > - Removed CLK_NR_CLKS from the clock binding.
> > 
> 
> All your patches seems to have odd commit msg.
> 
> > Signed-off-by: Cunhao Lu <1579567540@qq.com>

With code originating in the vendor kernel, it is nice to know what changed,
but I guess there is a tradeoff between brevity and more details.

I guess this could be shorted to something less verbose, like

+++++++++++++
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted to mainline rockchip clock and reset handling (xin24m input,
  don't introduce CLK_NR_CLKS, etc ]
Signed-off-by: Cunhao Lu <1579567540@qq.com>
+++++++++++++