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X-CSE-ConnectionGUID: GHpCuspEQ0mEk8W/3qGhbA== X-CSE-MsgGUID: DKmuK59dRJidK7j0KPW5gg== X-IronPort-AV: E=McAfee;i="6700,10204,11137"; a="30098696" X-IronPort-AV: E=Sophos;i="6.09,219,1716274800"; d="scan'208";a="30098696" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 16:28:01 -0700 X-CSE-ConnectionGUID: 2r360qDhToK1XvF2+XOO/Q== X-CSE-MsgGUID: U1Yp8Jb/RDenoJcqYspsSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,219,1716274800"; d="scan'208";a="51532661" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [10.125.108.184]) ([10.125.108.184]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2024 16:28:00 -0700 Message-ID: <33c34f2d-55cb-4b50-888d-1293ea2fa67d@intel.com> Date: Thu, 18 Jul 2024 16:27:59 -0700 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/15] cxl: add function for type2 cxl regs setup To: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org, netdev@vger.kernel.org, dan.j.williams@intel.com, martin.habets@xilinx.com, edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, richard.hughes@amd.com Cc: Alejandro Lucero References: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> <20240715172835.24757-3-alejandro.lucero-palau@amd.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <20240715172835.24757-3-alejandro.lucero-palau@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/15/24 10:28 AM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Create a new function for a type2 device initialising the opaque > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero > --- > drivers/cxl/pci.c | 28 ++++++++++++++++++++++++++++ > drivers/net/ethernet/sfc/efx_cxl.c | 3 +++ > include/linux/cxl_accel_mem.h | 1 + > 3 files changed, 32 insertions(+) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index e53646e9f2fb..b34d6259faf4 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include "cxlmem.h" > #include "cxlpci.h" > #include "cxl.h" > @@ -521,6 +522,33 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > return cxl_setup_regs(map); > } > > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) Function should go into cxl/core/pci.c > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); > + if (rc) > + return rc; > + > + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map); > + if (rc) > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + > + rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); dev_warn()? also maybe add the errno in the error emissioni. > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); > + > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index 4554dd7cca76..10c4fb915278 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -47,6 +47,9 @@ void efx_cxl_init(struct efx_nic *efx) > > res = DEFINE_RES_MEM_NAMED(0, EFX_CTPIO_BUFFER_SIZE, "ram"); > cxl_accel_set_resource(cxl->cxlds, res, CXL_ACCEL_RES_RAM); > + > + if (cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds)) > + pci_info(pci_dev, "CXL accel setup regs failed"); pci_warn()? although seems unnecesary since error emitted in cxl_pci_accel_setup_regs(). > } > > > diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h > index daf46d41f59c..ca7af4a9cefc 100644 > --- a/include/linux/cxl_accel_mem.h > +++ b/include/linux/cxl_accel_mem.h > @@ -19,4 +19,5 @@ void cxl_accel_set_dvsec(cxl_accel_state *cxlds, u16 dvsec); > void cxl_accel_set_serial(cxl_accel_state *cxlds, u64 serial); > void cxl_accel_set_resource(struct cxl_dev_state *cxlds, struct resource res, > enum accel_resource); > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); > #endif