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From: Jens Emil Schulz Ostergaard <jensemil.schulzostergaard@microchip.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	Horatiu Vultur <horatiu.vultur@microchip.com>,
	<o.rempel@pengutronix.de>,
	Steen Hegelund <Steen.Hegelund@microchip.com>,
	Daniel Machon <daniel.machon@microchip.com>,
	<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next] net: phy: micrel: Add support for lan9645x internal phy
Date: Tue, 27 Jan 2026 09:49:14 +0100	[thread overview]
Message-ID: <3540b83dbec35b7d2ffc370e517fe72340625dcf.camel@microchip.com> (raw)
In-Reply-To: <6f80050b-558c-4be3-89a0-a242ee528ea9@lunn.ch>

Hi Andrew,

On Fri, 2026-01-23 at 17:11 +0100, Andrew Lunn wrote:
> > +static int lan9645x_config_intr(struct phy_device *phydev)
> > +{
> > +     int err;
> > +
> > +     /* enable / disable interrupts */
> > +     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
> > +             /* This is an internal PHY of lan9645x and is not possible to
> > +              * change the polarity of irq sources in the OIC (CPU_INTR)
> > +              * found in lan9645x. Therefore change the polarity of the
> > +              * interrupt in the PHY from being active low instead of active
> > +              * high.
> > +              */
> > +             phy_write(phydev, LAN8804_CONTROL,
> > +                       LAN8804_CONTROL_INTR_POLARITY);
> > +
> > +             /* By default interrupt buffer is open-drain in which case the
> > +              * interrupt can be active only low. Therefore change the
> > +              * interrupt buffer to be push-pull to be able to change
> > +              * interrupt polarity.
> > +              */
> 
> It is not stated here, but i assume that there are multiple of these
> PHYs in the switch, and each PHY has its own independent connection to
> the parent interrupt controller? There is no interrupt sharing going
> on, which is common with discreet PHYs.
> 
>         Andrew

Yes you are right, there are 5 of these PHYs in the chip, each with their
on connection to the interrupt controller. It is similar to lan966x,
which has two internal PHYs of an older generation.

Thanks,
Emil


      reply	other threads:[~2026-01-27  8:49 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-23  7:50 [PATCH net-next] net: phy: micrel: Add support for lan9645x internal phy Jens Emil Schulz Østergaard
2026-01-23  8:57 ` Maxime Chevallier
2026-01-23 13:40   ` Jens Emil Schulz Ostergaard
2026-01-23  9:55 ` Oleksij Rempel
2026-01-23 15:12   ` Jens Emil Schulz Ostergaard
2026-01-23 16:11 ` Andrew Lunn
2026-01-27  8:49   ` Jens Emil Schulz Ostergaard [this message]

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