From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiner Kallweit Subject: [PATCH net-next 1/2] r8169: simplify RTL8169 PHY initialization Date: Wed, 19 Sep 2018 22:00:24 +0200 Message-ID: <35548e5c-2421-04b6-b6d7-335c1b7fb62d@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: "netdev@vger.kernel.org" To: David Miller , Realtek linux nic maintainers Return-path: Received: from mail-wr1-f65.google.com ([209.85.221.65]:36100 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727371AbeITBkC (ORCPT ); Wed, 19 Sep 2018 21:40:02 -0400 Received: by mail-wr1-f65.google.com with SMTP id e1-v6so7058415wrt.3 for ; Wed, 19 Sep 2018 13:00:32 -0700 (PDT) Content-Language: en-US Sender: netdev-owner@vger.kernel.org List-ID: PCI_LATENCY_TIMER is ignored on PCIe, therefore we have to do this for the PCI chips (version <= 06) only. Also we can move setting PCI_CACHE_LINE_SIZE. Signed-off-by: Heiner Kallweit --- drivers/net/ethernet/realtek/r8169.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 7f4647c58..a27bf5807 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -4046,16 +4046,13 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) rtl_hw_phy_config(dev); if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { + pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); + pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); netif_dbg(tp, drv, dev, "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); RTL_W8(tp, 0x82, 0x01); } - pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); - - if (tp->mac_version <= RTL_GIGA_MAC_VER_06) - pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); - if (tp->mac_version == RTL_GIGA_MAC_VER_02) { netif_dbg(tp, drv, dev, "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); -- 2.19.0