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Wed, 21 Oct 2026 12:20:30 -0700 (PDT) Received: from [198.18.0.1] ([152.175.97.38]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad85f56b03sm2573981a91.3.2026.10.21.12.20.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 12:20:29 -0700 (PDT) Message-ID: <38114050-123f-43df-ad74-6a27effd37a9@gmail.com> Date: Thu, 22 Oct 2026 03:20:19 +0800 X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v4] net: phy: realtek: Add support for JLSemi JL2101 and JL2121 PHYs To: Andrew Lunn Cc: Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261021170248.49264-1-cyan2254650260@gmail.com> <44fbfba4-edc1-453c-8e9c-8a6ddddb43ec@lunn.ch> Content-Language: en-US From: Pufan Jin In-Reply-To: <44fbfba4-edc1-453c-8e9c-8a6ddddb43ec@lunn.ch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2026/10/22 01:30, Andrew Lunn wrote: >> + PHY_ID_MATCH_MODEL(JLSEMI_JL21XX_PHYID), > Thanks for this change. > > https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html > > Since the merge window is open at the moment, patches will not be > accepted until it closes. > >> + .set_wol = rtl8211f_set_wol, >> + .get_wol = rtl8211f_get_wol, >> + .suspend = rtl8211f_suspend, >> + .resume = rtl8211f_resume, >> + .led_hw_is_supported = rtl8211x_led_hw_is_supported, >> + .led_hw_control_get = rtl8211f_led_hw_control_get, >> + .led_hw_control_set = rtl8211f_led_hw_control_set, > Have you tested these features? You have seen one register is > different. There might be others. > > Andrew Hi Andrew, Thanks for the clarification regarding the merge window. I will hold off submitting v4 until net-next reopens once the merge window closes. Regarding your question about testing: > Have you tested these features? You have seen one register is > different. There might be others. 1. WoL: On my ALINX AX7Z020B board, the INT/PME pin is not wired to the SoC as a system wakeup source, so I cannot test end-to-end Wake-on-LAN from system suspend. Furthermore, I probed the RTL8211F WoL registers (page 0xd8a and 0xd8c) directly on the hardware: writes do not stick and all registers read back as 0x0000. This confirms that the JL2121 does not share the RTL8211F WoL register map. Therefore, for v4 I have dropped .set_wol and .get_wol, and switched .probe to rtl821x_probe and .suspend/.resume to rtl821x_* (matching RTL8211F-VD) so the driver does not touch page 0xd8a. 2. Hardware LED control: I have already tested the LED hardware control on the physical AX7Z020B board. The RJ45 jack has green and yellow LEDs, and page 0xd04 reg 0x10 is indeed the active LED control register: - Boot default is 0xe251 (Mode B with 1000M+Act on LED2, 100M+Act on   LED1, 10M+Act on LED0). - Declaring leds child nodes in the board DTS successfully registered the   LEDs under /sys/class/leds/, and the netdev trigger confirmed   hardware offload ('offloaded: 1'). - Setting register 0x8000 (clearing all LED rules in Mode B) turns off   both green and yellow LEDs completely. - Setting 0xa000 (LED2 link 1000 only) turns on the green LED while yellow   remains off. - Bitfield manipulation verified that the green and yellow LEDs can be   independently toggled (e.g., single-LED blink and synchronous dual-LED   blink cycles). Therefore, the hardware LED registers and Mode B bitfields are identical to the RTL8211F. I will retain the verified .led_hw_* callbacks in v4. Thanks again for the review, Pufan