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[2a02:3100:a9db:600:159b:603:111e:5ffd]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-390e47a72d5sm8720211f8f.31.2025.03.01.07.01.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Mar 2025 07:01:28 -0800 (PST) Message-ID: <3854b3b6-365c-459e-ae97-ba88c804599e@gmail.com> Date: Sat, 1 Mar 2025 16:02:33 +0100 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 2/3] r8169: enable RTL8168H/RTL8168EP/RTL8168FP/RTL8125/RTL8126 LTR support To: Hau , nic_swsd , "andrew+netdev@lunn.ch" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , Bjorn Helgaas Cc: "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" References: <20250221071828.12323-439-nic_swsd@realtek.com> <20250221071828.12323-441-nic_swsd@realtek.com> <36d6094d-cc7c-4965-92ce-a271165a400a@gmail.com> <1544e50b9e4c4ee6a6d8ba6a777c2f07@realtek.com> Content-Language: en-US From: Heiner Kallweit Autocrypt: addr=hkallweit1@gmail.com; keydata= xsFNBF/0ZFUBEAC0eZyktSE7ZNO1SFXL6cQ4i4g6Ah3mOUIXSB4pCY5kQ6OLKHh0FlOD5/5/ sY7IoIouzOjyFdFPnz4Bl3927ClT567hUJJ+SNaFEiJ9vadI6vZm2gcY4ExdIevYHWe1msJF MVE4yNwdS+UsPeCF/6CQQTzHc+n7DomE7fjJD5J1hOJjqz2XWe71fTvYXzxCFLwXXbBiqDC9 dNqOe5odPsa4TsWZ09T33g5n2nzTJs4Zw8fCy8rLqix/raVsqr8fw5qM66MVtdmEljFaJ9N8 /W56qGCp+H8Igk/F7CjlbWXiOlKHA25mPTmbVp7VlFsvsmMokr/imQr+0nXtmvYVaKEUwY2g 86IU6RAOuA8E0J5bD/BeyZdMyVEtX1kT404UJZekFytJZrDZetwxM/cAH+1fMx4z751WJmxQ J7mIXSPuDfeJhRDt9sGM6aRVfXbZt+wBogxyXepmnlv9K4A13z9DVLdKLrYUiu9/5QEl6fgI kPaXlAZmJsQfoKbmPqCHVRYj1lpQtDM/2/BO6gHASflWUHzwmBVZbS/XRs64uJO8CB3+V3fa cIivllReueGCMsHh6/8wgPAyopXOWOxbLsZ291fmZqIR0L5Y6b2HvdFN1Xhc+YrQ8TKK+Z4R mJRDh0wNQ8Gm89g92/YkHji4jIWlp2fwzCcx5+lZCQ1XdqAiHQARAQABzSZIZWluZXIgS2Fs bHdlaXQgPGhrYWxsd2VpdDFAZ21haWwuY29tPsLBjgQTAQgAOBYhBGxfqY/yOyXjyjJehXLe ig9U8DoMBQJf9GRVAhsDBQsJCAcCBhUKCQgLAgQWAgMBAh4BAheAAAoJEHLeig9U8DoMSycQ AJbfg8HZEK0ljV4M8nvdaiNixWAufrcZ+SD8zhbxl8GispK4F3Yo+20Y3UoZ7FcIidJWUUJL axAOkpI/70YNhlqAPMsuudlAieeYZKjIv1WV5ucNZ3VJ7dC+dlVqQdAr1iD869FZXvy91KhJ wYulyCf+s4T9YgmLC6jLMBZghKIf1uhSd0NzjyCqYWbk2ZxByZHgunEShOhHPHswu3Am0ftt ePaYIHgZs+Vzwfjs8I7EuW/5/f5G9w1vibXxtGY/GXwgGGHRDjFM7RSprGOv4F5eMGh+NFUJ TU9N96PQYMwXVxnQfRXl8O6ffSVmFx4H9rovxWPKobLmqQL0WKLLVvA/aOHCcMKgfyKRcLah 57vGC50Ga8oT2K1g0AhKGkyJo7lGXkMu5yEs0m9O+btqAB261/E3DRxfI1P/tvDZpLJKtq35 dXsj6sjvhgX7VxXhY1wE54uqLLHY3UZQlmH3QF5t80MS7/KhxB1pO1Cpcmkt9hgyzH8+5org +9wWxGUtJWNP7CppY+qvv3SZtKJMKsxqk5coBGwNkMms56z4qfJm2PUtJQGjA65XWdzQACib 2iaDQoBqGZfXRdPT0tC1H5kUJuOX4ll1hI/HBMEFCcO8++Bl2wcrUsAxLzGvhINVJX2DAQaF aNetToazkCnzubKfBOyiTqFJ0b63c5dqziAgzsFNBF/0ZFUBEADF8UEZmKDl1w/UxvjeyAeX kghYkY3bkK6gcIYXdLRfJw12GbvMioSguvVzASVHG8h7NbNjk1yur6AONfbUpXKSNZ0skV8V fG+ppbaY+zQofsSMoj5gP0amwbwvPzVqZCYJai81VobefTX2MZM2Mg/ThBVtGyzV3NeCpnBa 8AX3s9rrX2XUoCibYotbbxx9afZYUFyflOc7kEpc9uJXIdaxS2Z6MnYLHsyVjiU6tzKCiVOU KJevqvzPXJmy0xaOVf7mhFSNQyJTrZpLa+tvB1DQRS08CqYtIMxRrVtC0t0LFeQGly6bOngr ircurWJiJKbSXVstLHgWYiq3/GmCSx/82ObeLO3PftklpRj8d+kFbrvrqBgjWtMH4WtK5uN5 1WJ71hWJfNchKRlaJ3GWy8KolCAoGsQMovn/ZEXxrGs1ndafu47yXOpuDAozoHTBGvuSXSZo ythk/0EAuz5IkwkhYBT1MGIAvNSn9ivE5aRnBazugy0rTRkVggHvt3/7flFHlGVGpBHxFUwb /a4UjJBPtIwa4tWR8B1Ma36S8Jk456k2n1id7M0LQ+eqstmp6Y+UB+pt9NX6t0Slw1NCdYTW gJezWTVKF7pmTdXszXGxlc9kTrVUz04PqPjnYbv5UWuDd2eyzGjrrFOsJEi8OK2d2j4FfF++ AzOMdW09JVqejQARAQABwsF2BBgBCAAgFiEEbF+pj/I7JePKMl6Fct6KD1TwOgwFAl/0ZFUC GwwACgkQct6KD1TwOgxUfg//eAoYc0Vm4NrxymfcY30UjHVD0LgSvU8kUmXxil3qhFPS7KA+ y7tgcKLHOkZkXMX5MLFcS9+SmrAjSBBV8omKoHNo+kfFx/dUAtz0lot8wNGmWb+NcHeKM1eb nwUMOEa1uDdfZeKef/U/2uHBceY7Gc6zPZPWgXghEyQMTH2UhLgeam8yglyO+A6RXCh+s6ak Wje7Vo1wGK4eYxp6pwMPJXLMsI0ii/2k3YPEJPv+yJf90MbYyQSbkTwZhrsokjQEaIfjrIk3 rQRjTve/J62WIO28IbY/mENuGgWehRlTAbhC4BLTZ5uYS0YMQCR7v9UGMWdNWXFyrOB6PjSu Trn9MsPoUc8qI72mVpxEXQDLlrd2ijEWm7Nrf52YMD7hL6rXXuis7R6zY8WnnBhW0uCfhajx q+KuARXC0sDLztcjaS3ayXonpoCPZep2Bd5xqE4Ln8/COCslP7E92W1uf1EcdXXIrx1acg21 H/0Z53okMykVs3a8tECPHIxnre2UxKdTbCEkjkR4V6JyplTS47oWMw3zyI7zkaadfzVFBxk2 lo/Tny+FX1Azea3Ce7oOnRUEZtWSsUidtIjmL8YUQFZYm+JUIgfRmSpMFq8JP4VH43GXpB/S OCrl+/xujzvoUBFV/cHKjEQYBxo+MaiQa1U54ykM2W4DnHb1UiEf5xDkFd4= In-Reply-To: <1544e50b9e4c4ee6a6d8ba6a777c2f07@realtek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 24.02.2025 17:33, Hau wrote: >> >> External mail : This email originated from outside the organization. Do not >> reply, click links, or open attachments unless you recognize the sender and >> know the content is safe. >> >> >> >> On 21.02.2025 08:18, ChunHao Lin wrote: >>> This patch will enable RTL8168H/RTL8168EP/RTL8168FP/RTL8125/RTL8126 >>> LTR support on the platforms that have tested with LTR enabled. >>> >> >> Where in the code is the check whether platform has been tested with LTR? >> > LTR is for L1,2. But L1 will be disabled when rtl_aspm_is_safe() return false. So LTR needs rtl_aspm_is_safe() > to return true. > >>> Signed-off-by: ChunHao Lin >>> --- >>> drivers/net/ethernet/realtek/r8169_main.c | 108 >>> ++++++++++++++++++++++ >>> 1 file changed, 108 insertions(+) >>> >>> diff --git a/drivers/net/ethernet/realtek/r8169_main.c >>> b/drivers/net/ethernet/realtek/r8169_main.c >>> index 731302361989..9953eaa01c9d 100644 >>> --- a/drivers/net/ethernet/realtek/r8169_main.c >>> +++ b/drivers/net/ethernet/realtek/r8169_main.c >>> @@ -2955,6 +2955,111 @@ static void rtl_disable_exit_l1(struct >> rtl8169_private *tp) >>> } >>> } >>> >>> +static void rtl_set_ltr_latency(struct rtl8169_private *tp) { >>> + switch (tp->mac_version) { >>> + case RTL_GIGA_MAC_VER_70: >>> + case RTL_GIGA_MAC_VER_71: >>> + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); >>> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcde8, 0x887a); >>> + r8168_mac_ocp_write(tp, 0xcdea, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); >>> + r8168_mac_ocp_write(tp, 0xcdee, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); >>> + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); >>> + r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); >>> + break; >>> + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: >>> + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd2, 0x889c); >>> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c30); >>> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcde8, 0x883e); >>> + r8168_mac_ocp_write(tp, 0xcdea, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdec, 0x889c); >>> + r8168_mac_ocp_write(tp, 0xcdee, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdf0, 0x8C09); >>> + r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); >>> + break; >>> + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_53: >>> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); >>> + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); >>> + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); >>> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); >>> + break; >>> + default: >>> + break; >>> + } >>> +} >>> + >>> +static void rtl_reset_pci_ltr(struct rtl8169_private *tp) { >>> + struct pci_dev *pdev = tp->pci_dev; >>> + u16 cap; >>> + >>> + pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap); >>> + if (cap & PCI_EXP_DEVCTL2_LTR_EN) { >>> + pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2, >>> + PCI_EXP_DEVCTL2_LTR_EN); >>> + pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, >>> + PCI_EXP_DEVCTL2_LTR_EN); >> >> I'd prefer that only PCI core deals with these registers (functions like >> pci_configure_ltr()). Any specific reason for this reset? Is it something which >> could be applicable for other devices too, so that the PCI core should be >> extended? >> > It is for specific platform. On that platform driver needs to do this to let LTR works. > >> +Bjorn and PCI list, to get an opinion from the PCI folks. >> >>> + } >>> +} >>> + >>> +static void rtl_enable_ltr(struct rtl8169_private *tp) { >>> + switch (tp->mac_version) { >>> + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: >>> + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000); >>> + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0)); >>> + r8168_mac_ocp_modify(tp, 0xe032, 0x0000, BIT(14)); >>> + break; >>> + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: >>> + case RTL_GIGA_MAC_VER_52 ... RTL_GIGA_MAC_VER_53: >>> + r8168_mac_ocp_modify(tp, 0xe0a2, 0x0000, BIT(0)); >>> + RTL_W8(tp, 0xb6, RTL_R8(tp, 0xb6) | BIT(0)); >>> + fallthrough; >>> + case RTL_GIGA_MAC_VER_51: >>> + r8168_mac_ocp_modify(tp, 0xe034, 0x0000, 0xc000); >>> + r8168_mac_ocp_write(tp, 0xe02c, 0x1880); >>> + r8168_mac_ocp_write(tp, 0xe02e, 0x4880); >>> + break; >>> + default: >>> + return; >>> + } >>> + >>> + rtl_set_ltr_latency(tp); >>> + >>> + /* chip can trigger LTR */ >>> + r8168_mac_ocp_modify(tp, 0xe032, 0x0003, BIT(0)); >>> + >>> + /* reset LTR to notify host */ >>> + rtl_reset_pci_ltr(tp); >>> +} >>> + >>> +static void rtl_disable_ltr(struct rtl8169_private *tp) { >>> + switch (tp->mac_version) { >>> + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_71: >>> + r8168_mac_ocp_modify(tp, 0xe032, 0x0003, 0); >>> + break; >>> + default: >>> + break; >>> + } >>> +} >>> + >>> static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, >>> bool enable) { >>> u8 val8; >>> @@ -2971,6 +3076,8 @@ static void rtl_hw_aspm_clkreq_enable(struct >> rtl8169_private *tp, bool enable) >>> tp->mac_version == RTL_GIGA_MAC_VER_43) >>> return; >>> >>> + rtl_enable_ltr(tp); >>> + >>> rtl_mod_config5(tp, 0, ASPM_en); >>> switch (tp->mac_version) { >>> case RTL_GIGA_MAC_VER_70: >>> @@ -4821,6 +4928,7 @@ static void rtl8169_down(struct rtl8169_private >>> *tp) >>> >>> rtl8169_cleanup(tp); >>> rtl_disable_exit_l1(tp); >>> + rtl_disable_ltr(tp); >> >> Any specific reason why LTR isn't configured just once, on driver load? >> > It is for device compatibility, I will check internally to see if we can remove it. > Thanks. Complementing what I wrote before: I would understand that reconfiguring LTR may be needed after a hw reset, when chip "forgets" settings. But is there a reason to disable the internal LTR config? IOW: What could happen if we omit rtl_disable_ltr()? > >>> rtl_prepare_power_down(tp); >>> >>> if (tp->dash_type != RTL_DASH_NONE) >