From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C5CE2D6E5A; Fri, 3 Jul 2026 16:37:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783096633; cv=none; b=Fv77UqAc1zIn7ZbX0tV+yCqzzVDH9Yi7BNn6fV/pWVFqxHVPiJebH+cG7FLUE50LaAolwIfB9uq96koX8h52b6zGysHiwsOX8p51g/9wnjxCkATrRInDGEWL+J+9tlkIWUx1KVZD0Y0FC9JqhPxVRo6MveZUPgSzpX788fyu5jA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783096633; c=relaxed/simple; bh=KxfPhjPFhReMVWNPeenydaELfDtLChm7M44+DEKl6+g=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bEeDul3FxP24rPBUT334AXY0JPu9qAf4gfv+XlNcA+NT3ZV6gtxpFf676XSSi9WkNgrfbSoyy/l0B6x0/PIJQY/hFpfVnd02ORZpXxbLDX7gazPnRVqbxYsuAfbJaVgDDoxzhNhuw44TZk7RobSiXRWdz1H8fATRcPh52rh5Zuo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=kFSwk4DT; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="kFSwk4DT" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=hmUlKrsXOGhOBBr628gJIn4v+9qb1yvV83sBQpdAcHc=; b=kFSwk4DTw4+gfIrH6tewSvXnSw Yz48PKw6lXxWGIAJPkCYagfkVvpBYYbHB/WQKzov2EyOoXvINyvasmDeo5DR25S/gy3leIWuE/V6L euuuFMEW9Cfm4tnktjUSP0J9yReBsA1ykCv24lx1WAH7biAaKP/Ix+nBiNKNL1XJYiYg=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wfgsk-00AZm5-Q4; Fri, 03 Jul 2026 18:36:50 +0200 Date: Fri, 3 Jul 2026 18:36:50 +0200 From: Andrew Lunn To: David Gibson Cc: Rosen Penev , netdev@vger.kernel.org, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jeff Garzik , open list Subject: Re: [PATCH net] net: emac: mal: fix W1C write race in ICINTSTAT clearing Message-ID: <3a9bdad9-3755-4efd-8de4-a3ce3ff30b69@lunn.ch> References: <20260702234923.1320412-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Jul 03, 2026 at 01:06:40PM +1000, David Gibson wrote: > On Thu, Jul 02, 2026 at 04:49:23PM -0700, Rosen Penev wrote: > > The ICINTSTAT register is write-1-to-clear (W1C). The read-modify-write > > pattern in both mal_txeob() and mal_rxeob() can lose interrupts: if a bit > > that should not be cleared is already asserted when mfdcri() reads the > > register, it is included in the read value, retained by the bitwise OR, and > > then written back as 1 - inadvertently clearing a pending but unhandled > > interrupt. > > > > Fix by writing only the specific bit to clear (ICINTSTAT_ICTX for TXEOB, > > ICINTSTAT_ICRX for RXEOB). W1C semantics guarantee that writing 0 to the > > other bits has no effect. > > Wow, it's a long time since I thought about the MAL. > > > Fixes: 1d3bb996481e ("Device tree aware EMAC driver") > > This doesn't appear correct. The lines in question were added by > fbcc4bacee30c ("ibm_newemac: MAL support for PowerPC 405EZ") > > > Assisted-by: opencode:big-pickle > > Signed-off-by: Rosen Penev > > Assuming ICINTSTAT is indeed a W1C register (or "read/clear" as I > believe they were termed in the 405 documentation) the change looks > correct. However, I no longer have access to the documentation that > would let me verify that. I would absolutely not trust an LLM to know > if that's the case, since it's a fairly arbitrary and specific detail > of an obscure CPU. I agree. If this is pure LLM, we need some form of verification. Andrew