From: 李志 <lizhi2@eswincomputing.com>
To: "Andrew Lunn" <andrew@lunn.ch>
Cc: devicetree@vger.kernel.org, andrew+netdev@lunn.ch,
davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
netdev@vger.kernel.org, pabeni@redhat.com,
mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com,
rmk+kernel@armlinux.org.uk,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, ningyu@eswincomputing.com,
linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com,
weishangjuan@eswincomputing.com
Subject: Re: Re: [PATCH v1 2/2] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
Date: Mon, 12 Jan 2026 14:55:45 +0800 (GMT+08:00) [thread overview]
Message-ID: <3c434477.2d22.19bb0fd3f21.Coremail.lizhi2@eswincomputing.com> (raw)
In-Reply-To: <1f553a6e-ca95-45e2-be14-96557a35e618@lunn.ch>
> -----原始邮件-----
> 发件人: "Andrew Lunn" <andrew@lunn.ch>
> 发送时间:2026-01-10 02:31:09 (星期六)
> 收件人: lizhi2@eswincomputing.com
> 抄送: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, weishangjuan@eswincomputing.com
> 主题: Re: [PATCH v1 2/2] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
>
> > + dwc_priv->eic7700_hsp_regmap =
> > + syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> > + "eswin,hsp-sp-csr");
> > + if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
> > return dev_err_probe(&pdev->dev,
> > - PTR_ERR(eic7700_hsp_regmap),
> > + PTR_ERR(dwc_priv->eic7700_hsp_regmap),
> > "Failed to get hsp-sp-csr regmap\n");
>
> In order to be backwards compatible, you cannot error out here,
> because old DT blobs won't have this property.
>
Thanks for the review.
We would like to clarify our understanding before changing the behavior.
'eswin,hsp-sp-csr' has been documented as a required property since the
initial EIC7700 DWMAC binding, and the existing driver already relies on
it for RX/TX clock delay programming. From our understanding, this
property is fundamental to correct MAC clock configuration on EIC7700,
rather than an optional enhancement.
Given this, could you please clarify whether we should still treat
eswin,hsp-sp-csr as optional at runtime purely for DT ABI robustness,
even though it is required by the binding and hardware design?
Once confirmed, we will update the driver and binding accordingly.
Thanks,
Li Zhi
prev parent reply other threads:[~2026-01-12 6:56 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-09 8:06 [PATCH v1 0/2] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing lizhi2
2026-01-09 8:08 ` [PATCH v1 1/2] dt-bindings: ethernet: eswin: add clock sampling control lizhi2
2026-01-09 18:27 ` Andrew Lunn
2026-01-10 18:26 ` Russell King (Oracle)
2026-01-11 4:05 ` Bo Gan
2026-01-12 7:05 ` 李志
2026-01-22 13:27 ` Andrew Lunn
2026-01-22 16:03 ` Russell King (Oracle)
2026-01-27 7:05 ` Min Lin
2026-01-27 13:40 ` Andrew Lunn
2026-01-12 6:00 ` 李志
2026-01-22 13:32 ` Andrew Lunn
2026-01-23 3:00 ` 李志
2026-01-23 3:19 ` Andrew Lunn
2026-01-23 7:39 ` Bo Gan
2026-01-23 9:52 ` 李志
2026-01-23 10:07 ` Krzysztof Kozlowski
2026-01-23 10:47 ` Bo Gan
2026-01-23 19:43 ` Andrew Lunn
2026-01-24 4:57 ` Bo Gan
2026-01-26 3:10 ` Min Lin
2026-01-26 18:29 ` Russell King (Oracle)
2026-01-27 6:14 ` Min Lin
2026-01-28 2:38 ` Bo Gan
2026-01-28 5:48 ` Min Lin
2026-02-03 6:06 ` Min Lin
2026-02-03 13:16 ` Andrew Lunn
2026-01-28 10:05 ` Krzysztof Kozlowski
2026-01-29 2:01 ` Bo Gan
2026-01-09 8:09 ` [PATCH v1 2/2] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing lizhi2
2026-01-09 18:31 ` Andrew Lunn
2026-01-12 6:55 ` 李志 [this message]
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