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Hermes SMTP Server) with ESMTPA ID 57d8cca23d589e339ba0a93d0327d3e8; Fri, 16 Oct 2026 01:09:45 +0000 (UTC) Message-ID: <3cb754f2-dc21-4de3-b245-b970719925fd@yahoo.com> Date: Fri, 16 Oct 2026 03:09:36 +0200 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH net-next v6 9/9] net: dsa: realtek: rtl8365mb: add support for RTL8367S-VB From: Mieczyslaw Nalewaj To: linusw@kernel.org, andrew@lunn.ch, olteanv@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, linux@armlinux.org.uk, luizluca@gmail.com, maxime.chevallier@bootlin.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <5a4715dd-89e0-4868-9ffb-c8fb73b18d04@yahoo.com> Content-Language: pl In-Reply-To: <5a4715dd-89e0-4868-9ffb-c8fb73b18d04@yahoo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailer: WebService/1.1.26740 mail.backend.jedi.jws.acl:role.jedi.acl.token.atz.jws.hermes.yahoo Add the RTL8367S-VB (chip ID 0x6642, version 0x0010) to the chip table. It is the first chip of family D, whose handling was added in the preceding patches, so this is the patch that makes it reachable. The SGMII/HSGMII SerDes of this chip sits on port 6 and the MII/TMII/RMII/RGMII interface on port 7, as on family C, but the external interface indices are one lower (EXT0 and EXT1 instead of EXT1 and EXT2). The chip reuses the existing initialization jam table. The chip has 8 ports, not 11. Cap priv->num_ports at RTL8365MB_D_MAX_NUM_PORTS for family D. This is a functional change: it sets ds->num_ports, the IRQ domain size and the bound of every loop over priv->num_ports. The L2 learning limit is the same as on family C (2112 entries), as given by the Realtek rtl8367 common API (rtl8367_common V1.4.2), so RTL8365MB_LEARN_LIMIT_MAX needs no per-family handling; only its comment is updated. Tested on a TP-Link Archer AX55 v1 (RTL8367S-VB, CPU port over HSGMII to an IPQ5018) with bridge VLAN filtering and per-port PVIDs. SGMII has also been seen working, but I no longer have the exact link partner and speed it was tested with, so treat it as lightly tested. RGMII mode has not yet been tested. Signed-off-by: Mieczyslaw Nalewaj --- drivers/net/dsa/realtek/rtl8365mb_main.c | 32 +++++++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c index a1155a7..dbf21a6 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -89,6 +89,12 @@ * things will work out-of-the-box for other chips, and a careful review of the * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be * one of the simpler chips. + * + * The RTL8367S-VB (chip ID 0x6642) is not part of the family listed above. It + * belongs to a newer generation, which this driver calls family D. Its + * registers differ in the VLAN table, the external interface speed and RGMII + * configuration and the SerDes, so the code paths specific to it are selected + * with rtl8365mb_get_family(). */ #include @@ -120,9 +126,10 @@ #define RTL8365MB_NUM_PHYREGS 32 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) #define RTL8365MB_MAX_NUM_PORTS 11 -/* Valid for the whole family except RTL8370B, which has 4160 entries. - * RTL8370B is mentioned in vendor code but it might not even belong - * to the same RTL8367C family. +#define RTL8365MB_D_MAX_NUM_PORTS 8 +/* Valid for the whole RTL8367C family (and for family D, RTL8367S-VB) + * except RTL8370B, which has 4160 entries. RTL8370B is mentioned in + * vendor code but it might not even belong to the same RTL8367C family. */ #define RTL8365MB_LEARN_LIMIT_MAX 2112 #define RTL8365MB_MAX_NUM_EXTINTS 3 @@ -887,6 +894,19 @@ static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = { .jam_table = rtl8365mb_init_jam_8365mb_vc, .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), }, + { + .name = "RTL8367S-VB", + .chip_id = 0x6642, + .chip_ver = 0x0010, + .family = RTL8365MB_FAMILY_D, + .extints = { + { 6, 0, PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, + { 7, 1, PHY_INTF(MII) | PHY_INTF(TMII) | + PHY_INTF(RMII) | PHY_INTF(RGMII) }, + }, + .jam_table = rtl8365mb_init_jam_8365mb_vc, + .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), + }, }; enum rtl8365mb_stp_state { @@ -3943,7 +3963,11 @@ static int rtl8365mb_detect(struct realtek_priv *priv) dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name); - priv->num_ports = RTL8365MB_MAX_NUM_PORTS; + if (rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D) + priv->num_ports = RTL8365MB_D_MAX_NUM_PORTS; + else + priv->num_ports = RTL8365MB_MAX_NUM_PORTS; + mb->priv = priv; ret = devm_mutex_init(priv->dev, &mb->sds_lock); -- 2.53.0