From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0544F43D518; Wed, 6 May 2026 14:20:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778077247; cv=none; b=LcZWKzf803N12y0cJ++iqTWljBXJb/w9hLhzPKddmJw4swnSKpoouPKwfNUKJSwod6/WKlCngLwkQpRkmm8Gn67qJOogCeqTE/lUHuext0PwBW/AEnAwuVfyNvLLSwnsjMY8wNOBfSt9ocnah88s0yJIN4KIDesQfRSgFjKgqA4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778077247; c=relaxed/simple; bh=dCNsi5z6SE2MWwj9xZX3J8gRDqSesA8VaakN/eL/kEI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=PqFKmVXbJyHr+ts1KwmzjMc12pwOXGMCSa8QvUj9NU8E47N7R2sAgKsZtcuHF1BXFqJaPjIjSJXP3M+4HNebUMcmDBTgjtkB12ZqPnE37edx4zrkbvaJ4aFZpPkIkKyDx2Ei+xNmhGb1fo2s/vLwuJAU9TRGt+W8N9tNRLsmzGA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=opZ83zhD; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="opZ83zhD" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=1TINjW2+GVZfWHKbu6bM194099KLPKEaQdFEP5VO8RU=; b=opZ83zhD6sjRhZ7vgFaALHMDtg yMrK1zc9GmBjDoW8m7f+apmZY4/bw8ws/7BIjjUvBWL3eGr2+CaCiB09M4COnVl9XwQH95NQrl262 e3VsH1fC3/lBBMuIlH1rUjT+xI53oA9VMCYeMYcxZxYvxxer0ML+kfNiaZ4gwy/8Y4Nc=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wKd6Q-001eSU-BM; Wed, 06 May 2026 16:19:54 +0200 Date: Wed, 6 May 2026 16:19:54 +0200 From: Andrew Lunn To: Xilin Wu Cc: Alex Elder , andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, Daniel Thompson , mohd.anwar@oss.qualcomm.com, a0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org, boon.khai.ng@altera.com, chenchuangyu@xiaomi.com, chenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org, hkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com, julianbraha@gmail.com, livelycarpet87@gmail.com, matthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc, prabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com, rohan.g.thomas@altera.com, sdf@fomichev.me, siyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com, wens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 10/12] net: stmmac: tc956x: add TC956x/QPS615 support Message-ID: <4015f47a-af62-441d-b1b8-a8598f963970@lunn.ch> References: <20260501155421.3329862-1-elder@riscstar.com> <20260501155421.3329862-11-elder@riscstar.com> <224E233C593EF171+8c8a43dd-5061-40f8-9eb7-f360eabf2ecc@radxa.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <224E233C593EF171+8c8a43dd-5061-40f8-9eb7-f360eabf2ecc@radxa.com> On Wed, May 06, 2026 at 08:59:01PM +0800, Xilin Wu wrote: > On 5/1/2026 11:54 PM, Alex Elder wrote: > > + /* AXI Configuration */ > > + axi = &td->axi; > > + axi->axi_lpi_en = 1; > > + axi->axi_wr_osr_lmt = 31; > > + axi->axi_rd_osr_lmt = 31; > > + /* All sizes (2^2..2^8) are supported */ > > + axi->axi_blen_regval = DMA_AXI_BLEN_MASK; > > + plat->axi = axi; > > + > > + plat->mac_port_sel_speed = speed; > > + plat->flags = STMMAC_FLAG_MULTI_MSI_EN | STMMAC_FLAG_TSO_EN; > > I got WoL working only after adding STMMAC_FLAG_USE_PHY_WOL here. I guess > it's required, since the driver clocks down the MAC/PMA/XPCS in its suspend > hook? Nice to see somebody testing WoL. In your testing, is it the PHY doing the WoL, or the MAC? I assume PHY. If i remember the DT correctly, the PHY interrupt is connected to a SoC GPIO, not a GPIO of this chip. So for your board, it is the SoCs GPIO controllers ability to perform the wake which is important. However, where the PHY interrupt is connected is a board design issue. Could the PHY interrupt be connected to the chip? Would the chip be able to wake the system? Should STMMAC_FLAG_USE_PHY_WOL be conditional? Andrew