PCI fix for some platforms

PCI fix for some platforms

[Andriy Korud]

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Hi,
i've noticed that on some platforms (noticed on PPC/XScale embedded) PCI cacheline size is not initialized properly and therefore card uses slow "PCI read memory" command instead of optimal "PCI read memory line", which cause serious bendwidth limitations in case of 3+ cards on single PCI bus.

Attached patch that fix this issue - please merge review.

regards,

--

Andriy Korud

 



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diff -ur prism54-cvs-latest/ksrc/islpci_dev.c prism54-cvs-latest-fix/ksrc/islpci_dev.c
--- prism54-cvs-latest/ksrc/islpci_dev.c	2004-05-29 18:06:49.000000000 +0300
+++ prism54-cvs-latest-fix/ksrc/islpci_dev.c	2004-06-29 18:52:02.006520304 +0300
@@ -773,6 +773,7 @@
 struct net_device *
 islpci_setup(struct pci_dev *pdev)
 {
+	u_int8_t cz;
 	islpci_private *priv;
 	struct net_device *ndev = alloc_etherdev(sizeof (islpci_private));
 
@@ -785,6 +786,12 @@
 	SET_NETDEV_DEV(ndev, &pdev->dev);
 #endif
 
+	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
+        if (csz == 0) {
+		csz = L1_CACHE_BYTES / sizeof(u_int32_t);
+		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
+	}
+
 	/* setup the structure members */
 	ndev->base_addr = pci_resource_start(pdev, 0);
 	ndev->irq = pdev->irq;

Re: PCI fix for some platforms

[Jeff Garzik]

Andriy Korud wrote:
> Hi,
> i've noticed that on some platforms (noticed on PPC/XScale embedded) PCI cacheline size is not initialized properly and therefore card uses slow "PCI read memory" command instead of optimal "PCI read memory line", which cause serious bendwidth limitations in case of 3+ cards on single PCI bus.
> 
> Attached patch that fix this issue - please merge review.


See pci_set_mwi()

	Jeff