* [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt
@ 2005-03-21 7:26 Michael Chan
2005-03-22 20:53 ` Jeff Garzik
2005-03-23 19:07 ` David S. Miller
0 siblings, 2 replies; 3+ messages in thread
From: Michael Chan @ 2005-03-21 7:26 UTC (permalink / raw)
To: David S. Miller; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 362 bytes --]
Add register read of PCI state register in tg3_interrupt() if status block's
updated bit is not set. This will flush the status block and confirm whether
the interrupt is ours or not. PCI ordering rules allow the interrupt to
arrive at the CPU ahead of the status block that may be posted at the
chipset.
Signed-off-by: Michael Chan <mchan@broadcom.com>
[-- Attachment #2: tg3-2.patch --]
[-- Type: application/octet-stream, Size: 750 bytes --]
diff -Nru 2/drivers/net/tg3.c 3/drivers/net/tg3.c
--- 2/drivers/net/tg3.c 2005-03-14 22:09:51.000000000 -0800
+++ 3/drivers/net/tg3.c 2005-03-14 22:24:35.000000000 -0800
@@ -2886,7 +2886,13 @@
spin_lock_irqsave(&tp->lock, flags);
- if (sblk->status & SD_STATUS_UPDATED) {
+ /* In INTx mode, it is possible for the interrupt to arrive at
+ * the CPU before the status block posted prior to the interrupt.
+ * Reading the PCI State register will confirm whether the
+ * interrupt is ours and will flush the status block.
+ */
+ if ((sblk->status & SD_STATUS_UPDATED) ||
+ !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
/*
* writing any value to intr-mbox-0 clears PCI INTA# and
* chip-internal interrupt pending events.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt
2005-03-21 7:26 [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt Michael Chan
@ 2005-03-22 20:53 ` Jeff Garzik
2005-03-23 19:07 ` David S. Miller
1 sibling, 0 replies; 3+ messages in thread
From: Jeff Garzik @ 2005-03-22 20:53 UTC (permalink / raw)
To: Michael Chan; +Cc: David S. Miller, netdev
Michael Chan wrote:
> Add register read of PCI state register in tg3_interrupt() if status block's
> updated bit is not set. This will flush the status block and confirm whether
> the interrupt is ours or not. PCI ordering rules allow the interrupt to
> arrive at the CPU ahead of the status block that may be posted at the
> chipset.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com
ACK
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt
2005-03-21 7:26 [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt Michael Chan
2005-03-22 20:53 ` Jeff Garzik
@ 2005-03-23 19:07 ` David S. Miller
1 sibling, 0 replies; 3+ messages in thread
From: David S. Miller @ 2005-03-23 19:07 UTC (permalink / raw)
To: Michael Chan; +Cc: netdev
On Sun, 20 Mar 2005 23:26:26 -0800
"Michael Chan" <mchan@broadcom.com> wrote:
> Add register read of PCI state register in tg3_interrupt() if status block's
> updated bit is not set. This will flush the status block and confirm whether
> the interrupt is ours or not. PCI ordering rules allow the interrupt to
> arrive at the CPU ahead of the status block that may be posted at the
> chipset.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com>
Applied, thanks Michael.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2005-03-21 7:26 [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt Michael Chan
2005-03-22 20:53 ` Jeff Garzik
2005-03-23 19:07 ` David S. Miller
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