From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jeff Garzik <jgarzik@pobox.com>
Subject: Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt
Date: Tue, 22 Mar 2005 15:53:29 -0500
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References: <B1508D50A0692F42B217C22C02D84972020F3E22@NT-IRVA-0741.brcm.ad.broadcom.com>
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Cc: "David S. Miller" <davem@davemloft.net>, netdev@oss.sgi.com
To: Michael Chan <mchan@broadcom.com>
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Michael Chan wrote:
> Add register read of PCI state register in tg3_interrupt() if status block's
> updated bit is not set. This will flush the status block and confirm whether
> the interrupt is ours or not. PCI ordering rules allow the interrupt to
> arrive at the CPU ahead of the status block that may be posted at the
> chipset.
> 
> Signed-off-by: Michael Chan <mchan@broadcom.com

ACK