* [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750
@ 2005-03-21 7:48 Michael Chan
2005-03-22 20:58 ` Jeff Garzik
2005-03-23 19:09 ` David S. Miller
0 siblings, 2 replies; 3+ messages in thread
From: Michael Chan @ 2005-03-21 7:48 UTC (permalink / raw)
To: David S. Miller; +Cc: netdev
[-- Attachment #1: Type: text/plain, Size: 177 bytes --]
Add unstable PLL clock workaround for 5750 Ax and Bx devices. The workaround
code is run just before entering D3hot state.
Signed-off-by: Michael Chan <mchan@broadcom.com>
[-- Attachment #2: tg3-5.patch --]
[-- Type: application/octet-stream, Size: 924 bytes --]
diff -Nru 5/drivers/net/tg3.c 6/drivers/net/tg3.c
--- 5/drivers/net/tg3.c 2005-03-17 17:15:40.000000000 -0800
+++ 6/drivers/net/tg3.c 2005-03-17 18:51:38.000000000 -0800
@@ -966,6 +966,7 @@
#define RESET_KIND_SUSPEND 2
static void tg3_write_sig_post_reset(struct tg3 *, int);
+static int tg3_halt_cpu(struct tg3 *, u32);
static int tg3_set_power_state(struct tg3 *tp, int state)
{
@@ -1124,6 +1125,17 @@
tg3_frob_aux_power(tp);
+ /* Workaround for unstable PLL clock */
+ if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
+ u32 val = tr32(0x7d00);
+
+ val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+ tw32(0x7d00, val);
+ if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
+ tg3_halt_cpu(tp, RX_CPU_BASE);
+ }
+
/* Finally, set the new power state. */
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750
2005-03-21 7:48 [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750 Michael Chan
@ 2005-03-22 20:58 ` Jeff Garzik
2005-03-23 19:09 ` David S. Miller
1 sibling, 0 replies; 3+ messages in thread
From: Jeff Garzik @ 2005-03-22 20:58 UTC (permalink / raw)
To: Michael Chan; +Cc: David S. Miller, netdev
Michael Chan wrote:
> Add unstable PLL clock workaround for 5750 Ax and Bx devices. The workaround
> code is run just before entering D3hot state.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com
ACK
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750
2005-03-21 7:48 [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750 Michael Chan
2005-03-22 20:58 ` Jeff Garzik
@ 2005-03-23 19:09 ` David S. Miller
1 sibling, 0 replies; 3+ messages in thread
From: David S. Miller @ 2005-03-23 19:09 UTC (permalink / raw)
To: Michael Chan; +Cc: netdev
On Sun, 20 Mar 2005 23:48:13 -0800
"Michael Chan" <mchan@broadcom.com> wrote:
> Add unstable PLL clock workaround for 5750 Ax and Bx devices. The workaround
> code is run just before entering D3hot state.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com>
Applied, thanks Michael.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2005-03-21 7:48 [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750 Michael Chan
2005-03-22 20:58 ` Jeff Garzik
2005-03-23 19:09 ` David S. Miller
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