From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jeff Garzik <jgarzik@pobox.com>
Subject: Re: [PATCH 2.6.11 5/8] tg3: Add unstable PLL workaround for 5750
Date: Tue, 22 Mar 2005 15:58:19 -0500
Message-ID: <424086EB.50302@pobox.com>
References: <B1508D50A0692F42B217C22C02D84972020F3E25@NT-IRVA-0741.brcm.ad.broadcom.com>
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Cc: "David S. Miller" <davem@davemloft.net>, netdev@oss.sgi.com
To: Michael Chan <mchan@broadcom.com>
In-Reply-To: <B1508D50A0692F42B217C22C02D84972020F3E25@NT-IRVA-0741.brcm.ad.broadcom.com>
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Michael Chan wrote:
> Add unstable PLL clock workaround for 5750 Ax and Bx devices. The workaround
> code is run just before entering D3hot state.
> 
> Signed-off-by: Michael Chan <mchan@broadcom.com

ACK