From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Friesen <cfriesen@nortel.com>
Subject: Re: RFC: NAPI packet weighting patch
Date: Tue, 21 Jun 2005 22:44:16 -0600
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Cc: Andi Kleen <ak@suse.de>, Rick Jones <rick.jones2@hp.com>,
        netdev@oss.sgi.com, davem@redhat.com
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To: Donald Becker <becker@scyld.com>
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Donald Becker wrote:
> On Wed, 22 Jun 2005, Andi Kleen wrote:
> 
> 
>>>While much has changed since then, the same basic parameters remain
>>>   - cache line size
>>
>>In 96 we had 32 byte cache lines. These days 64-128 are common,
>>with some 256 byte cache line systems around.
> 
> 
> Good point.
> I believe that the most common line size is 64 bytes for L1 cache.

If I recall, G4 chips are 32 bytes, and G5s are 128 bytes.  Most current 
x86 chips are 64 bytes though.

Chris