Re: [PATCH 5/9] [TULIP] Flush MMIO writes in reset sequence

[Jeff Garzik <jeff@garzik.org>]

Kyle McMartin wrote:
> From: Grant Grundler <grundler@parisc-linux.org>
> 
> The obvious safe registers to read is one from PCI config space.
> 
> Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
> ---
>  drivers/net/tulip/tulip_core.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
> index 6b54572..81905f4 100644
> --- a/drivers/net/tulip/tulip_core.c
> +++ b/drivers/net/tulip/tulip_core.c
> @@ -295,12 +295,14 @@ static void tulip_up(struct net_device *
>  
>  	/* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
>  	iowrite32(0x00000001, ioaddr + CSR0);
> +	pci_read_config_dword(tp->pdev, PCI_COMMAND, &i);  /* flush write */
>  	udelay(100);
>  
>  	/* Deassert reset.
>  	   Wait the specified 50 PCI cycles after a reset by initializing
>  	   Tx and Rx queues and the address filter list. */
>  	iowrite32(tp->csr0, ioaddr + CSR0);
> +	pci_read_config_dword(tp->pdev, PCI_COMMAND, &i);  /* flush write */
>  	udelay(100);

OK