Re: [PATCH 03/22] ixgb: Write RA register high word first, increment version

[Jeff Garzik <jgarzik@pobox.com>]

Kok, Auke wrote:
> We need to disable the AV bit before flushing the low register.
> 
> Signed-off-by: <aaron.k.salter@intel.com>
> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
> ---
> 
>  drivers/net/ixgb/ixgb_hw.c   |    3 ++-
>  drivers/net/ixgb/ixgb_main.c |    2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
> index 02089b6..ecbf458 100644
> --- a/drivers/net/ixgb/ixgb_hw.c
> +++ b/drivers/net/ixgb/ixgb_hw.c
> @@ -399,8 +399,9 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
>  	/* Zero out the other 15 receive addresses. */
>  	DEBUGOUT("Clearing RAR[1-15]\n");
>  	for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
> -		IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
> +		/* Write high reg first to disable the AV bit first */
>  		IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
> +		IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);

Are you sure the order is guaranteed even after this code change, when 
considering all manner of CPU and bus posted writes?

ACK if yes