netdev.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Jeff Garzik <jeff@garzik.org>
To: Brice Goglin <brice@myri.com>
Cc: netdev@vger.kernel.org
Subject: Re: [PATCH 2/3] myri10ge: more Intel chipsets providing aligned PCIe completions
Date: Wed, 11 Apr 2007 11:54:20 -0400	[thread overview]
Message-ID: <461D04AC.4020306@garzik.org> (raw)
In-Reply-To: <461BE3C3.3020800@myri.com>

Brice Goglin wrote:
> Add the Intel 5000 southbridge (aka Intel 6310/6311/6321ESB) PCIe ports
> and the Intel E30x0 chipsets to the whitelist of aligned PCIe completion.
> 
> Signed-off-by: Brice Goglin <brice@myri.com>
> ---
>  drivers/net/myri10ge/myri10ge.c |   17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> Index: linux-rc/drivers/net/myri10ge/myri10ge.c
> ===================================================================
> --- linux-rc.orig/drivers/net/myri10ge/myri10ge.c	2007-04-10 21:03:59.000000000 +0200
> +++ linux-rc/drivers/net/myri10ge/myri10ge.c	2007-04-10 21:04:35.000000000 +0200
> @@ -2487,6 +2487,10 @@
>  
>  #define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
>  #define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
> +#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510
> +#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b
> +#define PCI_DEVICE_ID_INTEL_E3000_PCIE	0x2779
> +#define PCI_DEVICE_ID_INTEL_E3010_PCIE	0x277a
>  #define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
>  #define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
>  
> @@ -2526,6 +2530,18 @@
>  				PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
>  				&& bridge->device <=
>  				PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
> +			    /* All Intel E3000/E3010 PCIE ports */
> +			    || (bridge->vendor == PCI_VENDOR_ID_INTEL
> +				&& (bridge->device ==
> +				    PCI_DEVICE_ID_INTEL_E3000_PCIE
> +				    || bridge->device ==
> +				    PCI_DEVICE_ID_INTEL_E3010_PCIE))
> +			    /* All Intel 6310/6311/6321ESB PCIE ports */
> +			    || (bridge->vendor == PCI_VENDOR_ID_INTEL
> +				&& bridge->device >=
> +				PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
> +				&& bridge->device <=
> +				PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
>  			    /* All Intel E5000 PCIE ports */
>  			    || (bridge->vendor == PCI_VENDOR_ID_INTEL
>  				&& bridge->device >=

though I'm applying this, long term this should probably move out of 
myri driver



  reply	other threads:[~2007-04-11 15:54 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-04-10 19:20 [PATCH 0/3] last myri10ge updates for 2.6.21 Brice Goglin
2007-04-10 19:21 ` [PATCH 1/3] myri10ge: fix management of the firmware 4KB boundary crossing restriction Brice Goglin
2007-04-11 15:55   ` Jeff Garzik
2007-04-10 19:21 ` [PATCH 2/3] myri10ge: more Intel chipsets providing aligned PCIe completions Brice Goglin
2007-04-11 15:54   ` Jeff Garzik [this message]
2007-04-11 18:39     ` Brice Goglin
2007-04-10 19:22 ` [PATCH 3/3] myri10ge: update driver version to 1.3.0-1.233 Brice Goglin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=461D04AC.4020306@garzik.org \
    --to=jeff@garzik.org \
    --cc=brice@myri.com \
    --cc=netdev@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).