Re: [PATCH 2/3] myri10ge: more Intel chipsets providing aligned PCIe completions

[Brice Goglin <brice@myri.com>]

Jeff Garzik wrote:
>> @@ -2526,6 +2530,18 @@
>>                  PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
>>                  && bridge->device <=
>>                  PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
>> +                /* All Intel E3000/E3010 PCIE ports */
>> +                || (bridge->vendor == PCI_VENDOR_ID_INTEL
>> +                && (bridge->device ==
>> +                    PCI_DEVICE_ID_INTEL_E3000_PCIE
>> +                    || bridge->device ==
>> +                    PCI_DEVICE_ID_INTEL_E3010_PCIE))
>> +                /* All Intel 6310/6311/6321ESB PCIE ports */
>> +                || (bridge->vendor == PCI_VENDOR_ID_INTEL
>> +                && bridge->device >=
>> +                PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
>> +                && bridge->device <=
>> +                PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
>>                  /* All Intel E5000 PCIE ports */
>>                  || (bridge->vendor == PCI_VENDOR_ID_INTEL
>>                  && bridge->device >=
>
> though I'm applying this, long term this should probably move out of
> myri driver

Right, we are worried about this already-too-long list. Even if we could
imagine having some dedicated functions/quirks or whatever to do this in
the PCI core, we are not sure somebody else will ever use this feature.
For now, we are exploring better ways to decide which firmware to use,
and we currently hope to remove the whitelist entirely in the near future.

Brice