* [PATCH 9/11][TG3]: Add ASPM workaround.
@ 2007-05-05 0:55 Michael Chan
2007-05-05 0:40 ` Jeff Garzik
0 siblings, 1 reply; 5+ messages in thread
From: Michael Chan @ 2007-05-05 0:55 UTC (permalink / raw)
To: davem, netdev
[TG3]: Add ASPM workaround.
This patch adds workaround to fix performance problems caused by slow
PCIE L1->L0 transitions on ICH8 platforms.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4fe38a0..b3681e4 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3019,6 +3019,15 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
}
}
+ if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
+ u32 val = tr32(0x7d28);
+ if (!netif_carrier_ok(tp->dev))
+ val = (val & ~0x0000ff00) | tp->pwrmgmt_thresh;
+ else
+ val |= 0x0000ff00;
+ tw32(0x7d28, val);
+ }
+
return err;
}
@@ -10004,6 +10013,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
}
+ if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
+ tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
return;
}
@@ -10131,6 +10142,14 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
/* bootcode if bit 18 is set */
if (cfg2 & (1 << 18))
tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
+
+ if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+ u32 cfg3;
+
+ tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
+ if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
+ tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
+ }
}
}
@@ -10997,6 +11016,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
*/
tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
+ if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
+ tp->pwrmgmt_thresh = tr32(0x7d28) & 0x0000ff00;
+
return err;
}
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index dcdfc08..d88a859 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1150,6 +1150,9 @@
#define VCPU_STATUS_INIT_DONE 0x04000000
#define VCPU_STATUS_DRV_RESET 0x08000000
+#define VCPU_CFGSHDW 0x00005104
+#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
+
/* Mailboxes */
#define GRCMBOX_BASE 0x00005600
#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
@@ -1593,6 +1596,9 @@
#define SHASTA_EXT_LED_MAC 0x00010000
#define SHASTA_EXT_LED_COMBO 0x00018000
+#define NIC_SRAM_DATA_CFG_3 0x00000d3c
+#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
+
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
@@ -2200,6 +2206,7 @@ struct tg3 {
#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
#define TG3_FLAG_ENABLE_ASF 0x00000020
+#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
#define TG3_FLAG_POLL_SERDES 0x00000080
#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
@@ -2288,6 +2295,7 @@ struct tg3 {
u32 grc_local_ctrl;
u32 dma_rwctrl;
u32 coalesce_mode;
+ u32 pwrmgmt_thresh;
/* PCI block */
u16 pci_chip_rev_id;
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 9/11][TG3]: Add ASPM workaround.
2007-05-05 0:55 [PATCH 9/11][TG3]: Add ASPM workaround Michael Chan
@ 2007-05-05 0:40 ` Jeff Garzik
2007-05-05 20:10 ` David Miller
0 siblings, 1 reply; 5+ messages in thread
From: Jeff Garzik @ 2007-05-05 0:40 UTC (permalink / raw)
To: Michael Chan; +Cc: davem, netdev
Michael Chan wrote:
> --- a/drivers/net/tg3.c
> +++ b/drivers/net/tg3.c
> @@ -3019,6 +3019,15 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
> }
> }
>
> + if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
> + u32 val = tr32(0x7d28);
> + if (!netif_carrier_ok(tp->dev))
> + val = (val & ~0x0000ff00) | tp->pwrmgmt_thresh;
> + else
> + val |= 0x0000ff00;
> + tw32(0x7d28, val);
> + }
> +
> return err;
> }
>
> @@ -10997,6 +11016,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
> */
> tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
>
> + if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
> + tp->pwrmgmt_thresh = tr32(0x7d28) & 0x0000ff00;
NAK -- magic numbers.
Please create a named constant for the register at 0x7d28.
Jeff
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 9/11][TG3]: Add ASPM workaround.
2007-05-05 0:40 ` Jeff Garzik
@ 2007-05-05 20:10 ` David Miller
2007-05-06 0:18 ` [PATCH revised " Michael Chan
0 siblings, 1 reply; 5+ messages in thread
From: David Miller @ 2007-05-05 20:10 UTC (permalink / raw)
To: jeff; +Cc: mchan, netdev
From: Jeff Garzik <jeff@garzik.org>
Date: Fri, 04 May 2007 20:40:09 -0400
> Michael Chan wrote:
> > --- a/drivers/net/tg3.c
> > +++ b/drivers/net/tg3.c
> > @@ -3019,6 +3019,15 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
> > }
> > }
> >
> > + if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
> > + u32 val = tr32(0x7d28);
> > + if (!netif_carrier_ok(tp->dev))
> > + val = (val & ~0x0000ff00) | tp->pwrmgmt_thresh;
> > + else
> > + val |= 0x0000ff00;
> > + tw32(0x7d28, val);
> > + }
> > +
> > return err;
> > }
> >
> > @@ -10997,6 +11016,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
> > */
> > tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
> >
> > + if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
> > + tp->pwrmgmt_thresh = tr32(0x7d28) & 0x0000ff00;
>
>
> NAK -- magic numbers.
>
> Please create a named constant for the register at 0x7d28.
Agree, please fix this patch up Michael.
Thanks.
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH revised 9/11][TG3]: Add ASPM workaround.
2007-05-05 20:10 ` David Miller
@ 2007-05-06 0:18 ` Michael Chan
2007-05-07 7:26 ` David Miller
0 siblings, 1 reply; 5+ messages in thread
From: Michael Chan @ 2007-05-06 0:18 UTC (permalink / raw)
To: David Miller; +Cc: jeff, netdev
[TG3]: Add ASPM workaround.
This patch adds workaround to fix performance problems caused by slow
PCIE L1->L0 transitions on ICH8 platforms.
Changed all magic numbers to constants as suggested by Jeff Garzik.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 59d6e74..da1ab01 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3019,6 +3019,16 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
}
}
+ if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
+ u32 val = tr32(PCIE_PWR_MGMT_THRESH);
+ if (!netif_carrier_ok(tp->dev))
+ val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
+ tp->pwrmgmt_thresh;
+ else
+ val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
+ tw32(PCIE_PWR_MGMT_THRESH, val);
+ }
+
return err;
}
@@ -10004,6 +10014,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
}
+ if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
+ tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
return;
}
@@ -10131,6 +10143,14 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
/* bootcode if bit 18 is set */
if (cfg2 & (1 << 18))
tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
+
+ if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+ u32 cfg3;
+
+ tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
+ if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
+ tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
+ }
}
}
@@ -10998,6 +11018,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
*/
tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
+ if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
+ tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
+ PCIE_PWR_MGMT_L1_THRESH_MSK;
+
return err;
}
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index dcdfc08..4d334cf 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1150,6 +1150,9 @@
#define VCPU_STATUS_INIT_DONE 0x04000000
#define VCPU_STATUS_DRV_RESET 0x08000000
+#define VCPU_CFGSHDW 0x00005104
+#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
+
/* Mailboxes */
#define GRCMBOX_BASE 0x00005600
#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
@@ -1507,6 +1510,8 @@
#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
#define PCIE_TRANS_CFG_LOM 0x00000020
+#define PCIE_PWR_MGMT_THRESH 0x00007d28
+#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
#define TG3_EEPROM_MAGIC 0x669955aa
#define TG3_EEPROM_MAGIC_FW 0xa5000000
@@ -1593,6 +1598,9 @@
#define SHASTA_EXT_LED_MAC 0x00010000
#define SHASTA_EXT_LED_COMBO 0x00018000
+#define NIC_SRAM_DATA_CFG_3 0x00000d3c
+#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
+
#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
@@ -2200,6 +2208,7 @@ struct tg3 {
#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
#define TG3_FLAG_ENABLE_ASF 0x00000020
+#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
#define TG3_FLAG_POLL_SERDES 0x00000080
#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
@@ -2288,6 +2297,7 @@ struct tg3 {
u32 grc_local_ctrl;
u32 dma_rwctrl;
u32 coalesce_mode;
+ u32 pwrmgmt_thresh;
/* PCI block */
u16 pci_chip_rev_id;
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH revised 9/11][TG3]: Add ASPM workaround.
2007-05-06 0:18 ` [PATCH revised " Michael Chan
@ 2007-05-07 7:26 ` David Miller
0 siblings, 0 replies; 5+ messages in thread
From: David Miller @ 2007-05-07 7:26 UTC (permalink / raw)
To: mchan; +Cc: jeff, netdev
From: "Michael Chan" <mchan@broadcom.com>
Date: Sat, 05 May 2007 17:18:29 -0700
> [TG3]: Add ASPM workaround.
>
> This patch adds workaround to fix performance problems caused by slow
> PCIE L1->L0 transitions on ICH8 platforms.
>
> Changed all magic numbers to constants as suggested by Jeff Garzik.
>
> Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
> Signed-off-by: Michael Chan <mchan@broadcom.com>
Applied.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2007-05-05 0:55 [PATCH 9/11][TG3]: Add ASPM workaround Michael Chan
2007-05-05 0:40 ` Jeff Garzik
2007-05-05 20:10 ` David Miller
2007-05-06 0:18 ` [PATCH revised " Michael Chan
2007-05-07 7:26 ` David Miller
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