From: Risto Suominen <risto.suominen@gmail.com>
To: netdev@vger.kernel.org
Subject: Fwd: [PATCH 002/002] de2104x: support for systems lacking cache coherence
Date: Mon, 9 Feb 2009 09:27:49 +0200 [thread overview]
Message-ID: <46e1c7760902082327s1c498ac3w56939960ac306426@mail.gmail.com> (raw)
In-Reply-To: <46e1c7760902071330i5362fe4fvd99fc7075fc666d3@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2844 bytes --]
---------- Forwarded message ----------
From: Risto Suominen <risto.suominen@gmail.com>
Date: 2009/2/7
Subject: [PATCH 002/002] de2104x: support for systems lacking cache coherence
To: Jeff Garzik <jgarzik@pobox.com>, lkml <linux-kernel@vger.kernel.org>
Add a configurable Descriptor Skip Length for systems that lack cache coherence.
Signed-off-by: Risto Suominen <Risto.Suominen@gmail.com>
---
The testing is done on kernel version 2.6.18.
--- drivers/net/tulip/Kconfig.org 2006-09-20 06:42:06.000000000 +0300
+++ drivers/net/tulip/Kconfig 2009-02-07 20:48:17.000000000 +0200
@@ -27,6 +27,18 @@ config DE2104X
To compile this driver as a module, choose M here. The module will
be called de2104x.
+config DE2104X_DSL
+ int "Descriptor Skip Length in 32 bit longwords"
+ depends on DE2104X
+ range 0 31
+ default 0
+ help
+ Setting this value allows to align ring buffer descriptors into their
+ own cache lines. Value of 4 corresponds to the typical 32 byte line
+ (the descriptor is 16 bytes). This is necessary on systems that lack
+ cache coherence, an example is PowerMac 5500. Otherwise 0 is safe.
+ Default is 0, and range is 0 to 31.
+
config TULIP
tristate "DECchip Tulip (dc2114x) PCI support"
depends on PCI
--- drivers/net/tulip/de2104x.c.org 2006-09-20 06:42:06.000000000 +0300
+++ drivers/net/tulip/de2104x.c 2009-02-07 15:04:04.000000000 +0200
@@ -82,6 +82,13 @@ MODULE_PARM_DESC (rx_copybreak, "de2104x
NETIF_MSG_RX_ERR | \
NETIF_MSG_TX_ERR)
+/* Descriptor skip length in 32 bit longwords. */
+#ifndef CONFIG_DE2104X_DSL
+#define DSL 0
+#else
+#define DSL CONFIG_DE2104X_DSL
+#endif
+
#define DE_RX_RING_SIZE 64
#define DE_TX_RING_SIZE 64
#define DE_RING_BYTES \
@@ -153,6 +160,7 @@ enum {
CmdReset = (1 << 0),
CacheAlign16 = 0x00008000,
BurstLen4 = 0x00000400,
+ DescSkipLen = (DSL << 2),
/* Rx/TxPoll bits */
NormalTxPoll = (1 << 0),
@@ -246,7 +254,7 @@ static const u32 de_intr_mask =
* Set the programmable burst length to 4 longwords for all:
* DMA errors result without these values. Cache align 16 long.
*/
-static const u32 de_bus_mode = CacheAlign16 | BurstLen4;
+static const u32 de_bus_mode = CacheAlign16 | BurstLen4 | DescSkipLen;
struct de_srom_media_block {
u8 opts;
@@ -266,6 +274,9 @@ struct de_desc {
__le32 opts2;
__le32 addr1;
__le32 addr2;
+#if DSL
+ __le32 skip[DSL];
+#endif
};
struct media_info {
[-- Attachment #2: de2104x-dsl.patch --]
[-- Type: text/x-diff, Size: 2182 bytes --]
Add a configurable Descriptor Skip Length for systems that lack cache coherence.
Signed-off-by: Risto Suominen <Risto.Suominen@gmail.com>
---
The testing is done on kernel version 2.6.18.
--- drivers/net/tulip/Kconfig.org 2006-09-20 06:42:06.000000000 +0300
+++ drivers/net/tulip/Kconfig 2009-02-07 20:48:17.000000000 +0200
@@ -27,6 +27,18 @@ config DE2104X
To compile this driver as a module, choose M here. The module will
be called de2104x.
+config DE2104X_DSL
+ int "Descriptor Skip Length in 32 bit longwords"
+ depends on DE2104X
+ range 0 31
+ default 0
+ help
+ Setting this value allows to align ring buffer descriptors into their
+ own cache lines. Value of 4 corresponds to the typical 32 byte line
+ (the descriptor is 16 bytes). This is necessary on systems that lack
+ cache coherence, an example is PowerMac 5500. Otherwise 0 is safe.
+ Default is 0, and range is 0 to 31.
+
config TULIP
tristate "DECchip Tulip (dc2114x) PCI support"
depends on PCI
--- drivers/net/tulip/de2104x.c.org 2006-09-20 06:42:06.000000000 +0300
+++ drivers/net/tulip/de2104x.c 2009-02-07 15:04:04.000000000 +0200
@@ -82,6 +82,13 @@ MODULE_PARM_DESC (rx_copybreak, "de2104x
NETIF_MSG_RX_ERR | \
NETIF_MSG_TX_ERR)
+/* Descriptor skip length in 32 bit longwords. */
+#ifndef CONFIG_DE2104X_DSL
+#define DSL 0
+#else
+#define DSL CONFIG_DE2104X_DSL
+#endif
+
#define DE_RX_RING_SIZE 64
#define DE_TX_RING_SIZE 64
#define DE_RING_BYTES \
@@ -153,6 +160,7 @@ enum {
CmdReset = (1 << 0),
CacheAlign16 = 0x00008000,
BurstLen4 = 0x00000400,
+ DescSkipLen = (DSL << 2),
/* Rx/TxPoll bits */
NormalTxPoll = (1 << 0),
@@ -246,7 +254,7 @@ static const u32 de_intr_mask =
* Set the programmable burst length to 4 longwords for all:
* DMA errors result without these values. Cache align 16 long.
*/
-static const u32 de_bus_mode = CacheAlign16 | BurstLen4;
+static const u32 de_bus_mode = CacheAlign16 | BurstLen4 | DescSkipLen;
struct de_srom_media_block {
u8 opts;
@@ -266,6 +274,9 @@ struct de_desc {
__le32 opts2;
__le32 addr1;
__le32 addr2;
+#if DSL
+ __le32 skip[DSL];
+#endif
};
struct media_info {
next parent reply other threads:[~2009-02-09 7:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <46e1c7760902071330i5362fe4fvd99fc7075fc666d3@mail.gmail.com>
2009-02-09 7:27 ` Risto Suominen [this message]
2009-02-09 7:45 ` [PATCH 002/002] de2104x: support for systems lacking cache coherence David Miller
2009-02-09 8:22 ` Risto Suominen
2009-02-09 8:29 ` David Miller
2009-02-09 8:35 ` Risto Suominen
2009-02-09 16:58 ` Krzysztof Halasa
2009-02-09 19:22 ` Risto Suominen
2009-02-09 22:51 ` David Miller
2009-02-10 1:45 ` Krzysztof Halasa
2009-02-10 1:50 ` David Miller
2009-02-10 23:21 ` David Miller
2009-02-11 12:18 ` Risto Suominen
2009-02-11 12:31 ` Risto Suominen
2009-02-11 21:39 ` David Miller
2009-02-13 3:42 ` Benjamin Herrenschmidt
2009-02-10 1:01 ` Andrew Morton
2009-02-10 1:07 ` David Miller
2009-02-10 7:16 ` Risto Suominen
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