Re: [PATCH 002/002] de2104x: support for systems lacking cache coherence

[Risto Suominen <risto.suominen@gmail.com>]

2009/2/9 David Miller <davem@davemloft.net>:
> From: Risto Suominen <risto.suominen@gmail.com>
> Date: Mon, 9 Feb 2009 09:27:49 +0200
>
>> Add a configurable Descriptor Skip Length for systems that lack cache coherence.
>>
>> Signed-off-by: Risto Suominen <Risto.Suominen@gmail.com>
>
> I really don't see why this patch could possibly be necessary.
>
Because it makes it work on my PowerMac 5500 ;)

> On systems that lack cache coherence:
>
> 1) {pci,dma}_alloc_{consistent,coherent}() give kernel mappings of
>   the buffer with the cache disabled.  Therefore the device and
>   and cpu see the correct data.
>
> 2) {pci,dma}_{map,unmap}_{single,sg}() do the appropriate cache
>   flushing.
>
>   Explicit syncing between cpu and device can be performed
>   using {pci,dma}_sync_{single,sg}() as needed.
>
Sounds good, but does not seem to help. My theory is that when the cpu
is writing to one descriptor, it accidentally overwrites another
descriptor, that has already been written to by the device, as there
is only a single dirty bit, that makes the whole cacheline to be
flushed.

> Therefore, this patch is superfluous.
>
Or everything else is. My solution does not cost a penny.

Risto