From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ayaz Abdulla Subject: [PATCH] forcedeth fix: tx/rx reset Date: Mon, 25 Aug 2008 13:36:58 -0400 Message-ID: <48B2EDBA.6070802@nvidia.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------070000060205060209010600" To: Jeff Garzik , Manfred Spraul , Andrew Morton , nedev Return-path: Received: from hqemgate04.nvidia.com ([216.228.112.152]:8283 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752135AbYHYUht (ORCPT ); Mon, 25 Aug 2008 16:37:49 -0400 Sender: netdev-owner@vger.kernel.org List-ID: This is a multi-part message in MIME format. --------------070000060205060209010600 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch keeps the HW reset for tx/rx asserted until DMA is enabled. This is to ensure that all tx/rx initialization (i.e ring setup) is finished before de-asserting the reset. Signed-off-by: Ayaz Abdulla --------------070000060205060209010600 Content-Type: text/plain; name="patch-forcedeth-reset" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="patch-forcedeth-reset" --- old/drivers/net/forcedeth.c 2008-08-25 13:02:17.000000000 -0400 +++ new/drivers/net/forcedeth.c 2008-08-25 13:02:20.000000000 -0400 @@ -233,7 +233,7 @@ NvRegTxRxControl = 0x144, #define NVREG_TXRXCTL_KICK 0x0001 #define NVREG_TXRXCTL_BIT1 0x0002 -#define NVREG_TXRXCTL_BIT2 0x0004 +#define NVREG_TXRXCTL_DMA_DISABLE 0x0004 #define NVREG_TXRXCTL_IDLE 0x0008 #define NVREG_TXRXCTL_RESET 0x0010 #define NVREG_TXRXCTL_RXCHECK 0x0400 @@ -1555,11 +1555,9 @@ u8 __iomem *base = get_hwbase(dev); dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); - writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); + writel(NVREG_TXRXCTL_DMA_DISABLE | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); pci_push(base); udelay(NV_TXRX_RESET_DELAY); - writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); - pci_push(base); } static void nv_mac_reset(struct net_device *dev) @@ -1570,7 +1568,7 @@ dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); - writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); + writel(NVREG_TXRXCTL_DMA_DISABLE | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); pci_push(base); /* save registers since they will be cleared on reset */ @@ -1589,9 +1587,6 @@ writel(temp1, base + NvRegMacAddrA); writel(temp2, base + NvRegMacAddrB); writel(temp3, base + NvRegTransmitPoll); - - writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); - pci_push(base); } static void nv_get_hw_stats(struct net_device *dev) --------------070000060205060209010600--