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(p200300f6ef1b2000944ccbc71e1c2c47.dip0.t-ipconnect.de. [2003:f6:ef1b:2000:944c:cbc7:1e1c:2c47]) by smtp.gmail.com with ESMTPSA id e13-20020a170906c00d00b00a2a1bbda0a6sm15497995ejz.175.2024.01.24.03.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 03:28:23 -0800 (PST) Message-ID: <49c0375637372ccae122f2abd2b992406bb40a5c.camel@gmail.com> Subject: Re: [PATCH v2 2/2] net: phy: adin: add recovered clock output From: Nuno =?ISO-8859-1?Q?S=E1?= To: Fabian Pfitzner , Michael Hennerich , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: kernel@pengutronix.de, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Date: Wed, 24 Jan 2024 12:31:38 +0100 In-Reply-To: <20240124102554.1327853-2-f.pfitzner@pengutronix.de> References: <20240122110311.2725036-1-f.pfitzner@pengutronix.de> <20240124102554.1327853-2-f.pfitzner@pengutronix.de> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-01-24 at 11:25 +0100, Fabian Pfitzner wrote: > The ADIN1300 offers three distinct output clocks which can be accessed > through the GP_CLK pin. The DT only offers two of the possible options > and thus the 125MHz-recovered output clock is missing. >=20 > As there is no other way to configure this pin than through the DT it > should be possible to do so for all available outputs. >=20 > Signed-off-by: Fabian Pfitzner > --- Reviewed-by: Nuno Sa > =C2=A0drivers/net/phy/adin.c | 2 ++ > =C2=A01 file changed, 2 insertions(+) >=20 > diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c > index 2e1a46e121d9..b1ed6fd24763 100644 > --- a/drivers/net/phy/adin.c > +++ b/drivers/net/phy/adin.c > @@ -508,6 +508,8 @@ static int adin_config_clk_out(struct phy_device *phy= dev) > =C2=A0 sel |=3D ADIN1300_GE_CLK_CFG_25; > =C2=A0 } else if (strcmp(val, "125mhz-free-running") =3D=3D 0) { > =C2=A0 sel |=3D ADIN1300_GE_CLK_CFG_FREE_125; > + } else if (strcmp(val, "125mhz-recovered") =3D=3D 0) { > + sel |=3D ADIN1300_GE_CLK_CFG_RCVR_125; > =C2=A0 } else if (strcmp(val, "adaptive-free-running") =3D=3D 0) { > =C2=A0 sel |=3D ADIN1300_GE_CLK_CFG_HRT_FREE; > =C2=A0 } else {