From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Dumazet <eric.dumazet@gmail.com>
Subject: Re: arm: Optimization for ethernet MAC handling at91_ether.c
Date: Tue, 12 Jan 2010 20:24:43 +0100
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To: James Kosin <JKosin@intcomgrp.com>
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Le 12/01/2010 20:03, James Kosin a =E9crit :
>=20
> Scratch that.  The interrupt doesn't queue up or send another packet =
directly.  So, it wouldn't help on performance here.  But, may in other=
 implementations that queue/transmit packets in the ISR.  At least in t=
he case where the transmitter is limited to one.
>=20

It could, at least on SMP. tx completion wakes a blocked sender, while
this cpu continue with RX handling (possibly expensive)

But even on UP, doing tx completion before rx handling allows
a better reuse of skb just freed (and partly present in cpu cache, if a=
vailable).

Start of IRQ

1) tx completion
    -> free a skb

2) rx handling:
    -> allocate an skb, kmalloc() reuses previous one, still in cpu cac=
he.

End of IRQ