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From: Wolfgang Grandegger <wg-5Yr1BZd7O62+XT7JhA+gdA@public.gmane.org>
To: Oliver Hartkopp <socketcan-fJ+pQTUTwRTk1uMJSBkQmQ@public.gmane.org>
Cc: SocketCAN Core Mailing List
	<socketcan-core-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org>,
	Linux Netdev List
	<netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	David Miller <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>,
	stable-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Subject: Re: [PATCH] Fix SJA1000 command register writes on SMP systems
Date: Mon, 17 May 2010 16:29:56 +0200	[thread overview]
Message-ID: <4BF152E4.1060306@grandegger.com> (raw)
In-Reply-To: <4BF12321.6080506-fJ+pQTUTwRTk1uMJSBkQmQ@public.gmane.org>

Hi Oliver,

On 05/17/2010 01:06 PM, Oliver Hartkopp wrote:
> The SJA1000 command register is concurrently written in the rx-path to free
> the receive buffer _and_ in the tx-path to start the transmission.
> On SMP systems this leads to a write stall in the tx-path, which can be
> solved by adding some locking for the command register in the SMP case.

We should explain why a write stall can happen. Here is the relavant
part from the SJA1000 data sheet, 6.4.4 COMMAND REGISTER (CMR):

"Between two commands at least one internal clock cycle is needed in
order to proceed. The internal clock is half of the external oscillator
frequency."

Wolfgang.

  parent reply	other threads:[~2010-05-17 14:29 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-05-17 11:06 [PATCH] Fix SJA1000 command register writes on SMP systems Oliver Hartkopp
     [not found] ` <4BF12321.6080506-fJ+pQTUTwRTk1uMJSBkQmQ@public.gmane.org>
2010-05-17 14:29   ` Wolfgang Grandegger [this message]
     [not found]     ` <4BF152E4.1060306-5Yr1BZd7O62+XT7JhA+gdA@public.gmane.org>
2010-05-17 19:47       ` Oliver Hartkopp
     [not found]         ` <4BF19D5B.1070604-fJ+pQTUTwRTk1uMJSBkQmQ@public.gmane.org>
2010-05-17 20:04           ` Wolfgang Grandegger

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