From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wolfgang Grandegger Subject: Re: [PATCH] Fix SJA1000 command register writes on SMP systems Date: Mon, 17 May 2010 16:29:56 +0200 Message-ID: <4BF152E4.1060306@grandegger.com> References: <4BF12321.6080506@hartkopp.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: SocketCAN Core Mailing List , Linux Netdev List , David Miller , stable-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org To: Oliver Hartkopp Return-path: In-Reply-To: <4BF12321.6080506-fJ+pQTUTwRTk1uMJSBkQmQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: socketcan-core-bounces-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org Errors-To: socketcan-core-bounces-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org List-Id: netdev.vger.kernel.org Hi Oliver, On 05/17/2010 01:06 PM, Oliver Hartkopp wrote: > The SJA1000 command register is concurrently written in the rx-path to free > the receive buffer _and_ in the tx-path to start the transmission. > On SMP systems this leads to a write stall in the tx-path, which can be > solved by adding some locking for the command register in the SMP case. We should explain why a write stall can happen. Here is the relavant part from the SJA1000 data sheet, 6.4.4 COMMAND REGISTER (CMR): "Between two commands at least one internal clock cycle is needed in order to proceed. The internal clock is half of the external oscillator frequency." Wolfgang.