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From: "Frantisek Rysanek" <Frantisek.Rysanek@post.cz>
To: netdev@vger.kernel.org
Cc: P.B.Cheblakov@inp.nsk.su, urs@isnogud.escape.de
Subject: [PATCH] CAN, sja1000, plx_pci.c : some device ID's for Advantech hardware
Date: Tue, 14 Jun 2011 17:01:15 +0200	[thread overview]
Message-ID: <4DF793DB.6863.5434F06B@Frantisek.Rysanek.post.cz> (raw)

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Dear Everyone,

attached you'll find a patch that adds support for the following 
hardware by Advantech:
PCI-1680 = dual-port PCI card
UNO-2052 = fanless PC (Geode-based) with 2x SJA1000 onboard via PCI

The patch consists of just some added PCI ID's, plus a one-liner 
bugfix (?): an added delay in plx_pci_check_sja1000() between the PLX 
reset and the SJA reset, giving the SJA more time to become ready for 
the switch to Pelican mode.

Tested using cansend+candump in Debian 6.
I was amazed that all the necessary bits are included "out of the 
box" in Sarge: support for CAN in "ip", libc headers etc.

Thanks for your excellent work, and for including the CAN subsystem 
in the vanilla mainline :-) It's a relief to have an official CAN 
stack in the vanilla kernel - no need to work out of tree anymore.

Frank Rysanek

P.S.: A quick Google survey of PCI-based CAN hardware (boards) from 
various vendors has revealed that
1) Advantech has some new models (PCI-1682 and PCM-3680*I*) 
    that use a Xilinx FPGA instead of the trusty old PLX bridges,
    and for which there is no register-level documentation
2) similarly, I've found a neat dual-port MiniPCI board from 
   Peak System Technik, apparently using a Lattice chip for the 
   same purpose... (likely with an open-source "character device" 
   driver from Peak, along with an additional user-space SDK)
I assume these general-purpose FPGA-based bridge devices are cheaper 
than the dedicated PLX silicon, but the change sadly does away with a 
great deal of homogenity that used to come with the slave bridges by 
PLX. I haven't put my hands on either of that new hardware, but I 
expect that the two SJA chips will still be visible as BAR's on the 
PCI bus. Hopefully there isn't much to get wrong in this kind of 
design...


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   ---- File information -----------
     File:  2.6.39_adv-pci-can.patch
     Date:  14 Jun 2011, 11:39
     Size:  2703 bytes.
     Type:  Unknown

[-- Attachment #3: 2.6.39_adv-pci-can.patch --]
[-- Type: Application/Octet-stream, Size: 2703 bytes --]

--- drivers/net/can/sja1000/Kconfig.old	2011-06-14 09:31:38.000000000 +0000
+++ drivers/net/can/sja1000/Kconfig	2011-06-14 09:28:08.000000000 +0000
@@ -58,6 +58,7 @@
 	   - esd CAN-PCIe/2000
 	   - Marathon CAN-bus-PCI card (http://www.marathon.ru/)
 	   - TEWS TECHNOLOGIES TPMC810 card (http://www.tews.com/)
+	   - Advantech PCI-1680 and UNO-2052 (http://www.advantech.com)
 
 config CAN_TSCAN1
 	tristate "TS-CAN1 PC104 boards"
--- drivers/net/can/sja1000/plx_pci.c.old	2011-06-10 15:21:41.000000000 +0000
+++ drivers/net/can/sja1000/plx_pci.c	2011-06-14 09:36:30.000000000 +0000
@@ -43,7 +43,8 @@
 			"TEWS TECHNOLOGIES TPMC810, "
 			"esd CAN-PCI/CPCI/PCI104/200, "
 			"esd CAN-PCI/PMC/266, "
-			"esd CAN-PCIe/2000")
+			"esd CAN-PCIe/2000,"
+                        "Advantech PCI-1680 & UNO-2052");
 MODULE_LICENSE("GPL v2");
 
 #define PLX_PCI_MAX_CHAN 2
@@ -126,6 +127,10 @@
 #define TEWS_PCI_VENDOR_ID		0x1498
 #define TEWS_PCI_DEVICE_ID_TMPC810	0x032A
 
+#define ADVANTECH_PCI_VENDOR_ID		0x13FE
+#define ADVANTECH_PCI1680_DEVICE_ID	0x1680
+#define ADVANTECH_UNO2052_DEVICE_ID	0x2052
+
 static void plx_pci_reset_common(struct pci_dev *pdev);
 static void plx_pci_reset_marathon(struct pci_dev *pdev);
 static void plx9056_pci_reset_common(struct pci_dev *pdev);
@@ -209,6 +214,22 @@
 	/* based on PLX9030 */
 };
 
+static struct plx_pci_card_info plx_pci_card_info_pci1680 __devinitdata = {
+	"Advantech PCI-1680", 2,
+	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
+	{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
+	&plx_pci_reset_common
+	/* based on PLX PCI9030 */
+};
+
+static struct plx_pci_card_info plx_pci_card_info_uno2052 __devinitdata = {
+	"Advantech UNO-2052", 2,
+	PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
+	{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
+	&plx_pci_reset_common
+	/* based on PLX PCI9052 */
+};
+
 static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
 	{
 		/* Adlink PCI-7841/cPCI-7841 */
@@ -280,6 +301,20 @@
 		0, 0,
 		(kernel_ulong_t)&plx_pci_card_info_tews
 	},
+	{
+		/* Advantech PCI-1680 */
+		ADVANTECH_PCI_VENDOR_ID, ADVANTECH_PCI1680_DEVICE_ID,
+		ADVANTECH_PCI_VENDOR_ID, PCI_ANY_ID,
+		0, 0,
+		(kernel_ulong_t)&plx_pci_card_info_pci1680
+	},
+	{
+		/* Advantech UNO-2052 */
+		ADVANTECH_PCI_VENDOR_ID, ADVANTECH_UNO2052_DEVICE_ID,
+		PCI_ANY_ID, PCI_ANY_ID,
+		0, 0,
+		(kernel_ulong_t)&plx_pci_card_info_uno2052
+	},
 	{ 0,}
 };
 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
@@ -303,6 +338,9 @@
 {
 	int flag = 0;
 
+        /* Give the SJA chip some time to finish its reset (invoked via PLX chip) */
+        mdelay(100);
+
 	/*
 	 * Check registers after hardware reset (the Basic mode)
 	 * See states on p. 10 of the Datasheet.

                 reply	other threads:[~2011-06-14 15:01 UTC|newest]

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