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Fri, 24 Jul 2026 08:08:08 -0700 (PDT) X-Received: by 2002:a05:690c:4c06:b0:81c:d9d0:8d6d with SMTP id 00721157ae682-81f4c3534fcmr25155797b3.57.1784905688193; Fri, 24 Jul 2026 08:08:08 -0700 (PDT) Received: from [192.168.0.116] ([124.123.146.251]) by smtp.gmail.com with ESMTPSA id 00721157ae682-81f65932eeesm1119767b3.48.2026.07.24.08.08.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 08:08:07 -0700 (PDT) Message-ID: <4b75ee6a-bbfc-4079-b617-4ba366f2c439@oss.qualcomm.com> Date: Fri, 24 Jul 2026 20:37:57 +0530 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] net: wwan: qcom_bam_dmux: Alloc RX buffers as a single coherent block To: Stephan Gerhold Cc: Stephan Gerhold , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Sergey Ryazanov , Johannes Berg , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, chris.lew@oss.qualcomm.com, Deepak Kumar Singh References: <20260714-qcom-bam-dmux-vmid-ext-v1-0-3f29da7cca76@oss.qualcomm.com> <20260714-qcom-bam-dmux-vmid-ext-v1-2-3f29da7cca76@oss.qualcomm.com> Content-Language: en-US From: Vishnu Santhosh In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Pq6jqQM3 c=1 sm=1 tr=0 ts=6a637fd9 cx=c_pps a=72HoHk1woDtn7btP4rdmlg==:117 a=K/78aEDNEn2Q/Yuv7mVN5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=lNWbMoYigRjAFYUbelMA:9 a=QEXdDO2ut3YA:10 a=kA6IBgd4cpdPkAWqgNAz:22 X-Proofpoint-GUID: aDo0SYNbASB1guNvX_t-rvlU7TSg4qDa X-Proofpoint-ORIG-GUID: aDo0SYNbASB1guNvX_t-rvlU7TSg4qDa X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNiBTYWx0ZWRfX0VC0vU+vCTRJ 6+aurZWVHbdpd0kcTHZjQ/oA+TC4vOtKYSbh0rXoFq+55vy9f9SHmWNQePR0yjwenDEGIoTz0kQ IX8ZPTHMhtY3sWbVq+28pFru7XUzoeM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNiBTYWx0ZWRfX5kCcoS2vmPG9 nZi02VScP04f9XA0S6l390IJLh506vguAuGyPG4zzF//nstdyFVuZ+Hz2AijhM/Nj20oJV6l6J7 Za7z0CRtmyP4RD37aoIM6uMRMAlLfb8WJAJY3ak/fQXa4kX4HJGq0SIMwk1AZTxu64aYmrodcZn wZfaLN1+o3FbNDNdVI0zWLXrjW2jdNzWjEKKDFZIrzXFD913iHUGkfrJPNcn/C7u3eUIw8zUQi+ 9vZr3lmZrmob5GHOc95LPI8mLjAVFw+nrinJz/VpdP8HGyYPzVZKe7KaYZniKAN9zj0SAtc1oTM 3BeCYRdUxUtsMvenu4re7CQa5cKUm1v1xjqzddrIu96pY5ObmH7AzIJa3BTy9ucjNP5QP9Hwk+P ndo1LGkgbRAsFeZR+Pp3d7q33SSDGixHWO/uM0I9NpPHRRgHaLKFq5mykiu+Vni56FV4T+3qDbI NNTw289Vbj1PZP17Q7A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240136 On 24-07-2026 03:04 pm, Stephan Gerhold wrote: > On Fri, Jul 24, 2026 at 10:16:31AM +0530, Vishnu Santhosh wrote: >> On 14-07-2026 01:05 pm, Stephan Gerhold wrote: >>> On Tue, Jul 14, 2026 at 11:02:32AM +0530, Vishnu Santhosh wrote: >>>> On Qualcomm SoCs where the modem (e.g. the mDSP on Shikra, VMID 43 / >>>> NAV) is the AXI master for BAM-DMUX RX transfers and the XPU enforces >>>> per-region access control, each individually DMA-mapped RX buffer >>>> requires its own XPU resource group (RG). With ~16 RGs available, the >>>> 32 per-buffer dma_map_single() calls exhaust the table and the first >>>> inbound transfer faults with an XPU violation. >>>> >>>> BAM-DMUX is a singleton (exactly one instance per SoC), so the >>>> destination VMID does not need to be a DT property; it is looked up >>>> from the compatible string's match data instead. Add struct >>>> bam_dmux_data with a single vmid field, and a shikra_data instance >>>> hardcoding QCOM_SCM_VMID_NAV for qcom,shikra-bam-dmux. >>>> >>>> When match data is present, allocate all BAM_DMUX_NUM_SKB RX buffers as >>>> a single contiguous dma_alloc_coherent() block and SCM-assign that >>>> block to HLOS plus the VMID once at probe. This reduces RG consumption >>>> from 32 to 1. The block is never reclaimed across a modem power cycle >>>> (bam_dmux_power_off() does not touch it), so the probe-time assignment >>>> covers every subsequent restart without re-assigning or reclaiming. It >>>> is reclaimed to HLOS only once, at remove or on a probe error, and if >>>> that reclaim fails it is leaked rather than returned to the page >>>> allocator. >>>> >>>> Each rx_skbs[] slot is pre-assigned its virtual and DMA address from >>>> the block, so no per-buffer mapping is needed at power-on. Because the >>>> coherent block is not page-backed, received payload is copied into a >>>> regular netdev skb before handoff to the network stack; this is an >>>> unavoidable extra copy on the XPU-enforced RX path. >>>> >>>> Platforms without match data are unaffected: rx_virt stays NULL, no >>>> coherent memory is allocated, and the per-buffer dma_map_single() path >>>> is unchanged. >>>> >>>> Co-developed-by: Deepak Kumar Singh >>>> Signed-off-by: Deepak Kumar Singh >>>> Signed-off-by: Vishnu Santhosh >>> So how do you handle TX buffers? Right now, they are just passed on from >>> the net subsystem. There can be up to 32 TX buffers in progress as well. >>> >>> Overall, I have mixed feelings about this patch. It looks reasonably >>> simple, but fundamentally I don't understand why we need to go back to >>> the old days of implementing protection using a highly limited MPU (in >>> your case: the xPU). >>> >>> Why does the setup of BAM-DMUX differ e.g. from the setup for the crypto >>> engine? Crypto is also using bam-dma, but it avoids this inflexibility >>> by making use of the &apps_smmu. Is BAM-DMUX not covered by the SMMU? Or >>> did you just decide to bypass the SMMU in this case? (If so: Why?) >> I checked with secure systems team on this. Crypto BAM is >> behind apps_smmu, so protection is enforced through the SMMU's Stage-2 >> page tables. >> >> A2 BAM (used by BAM-DMUX) is present in secure domain and does not >> support Stage-2 translation on this SoC, and there is no IOMMU domain >> that can be attached to it. The only protection mechanism available is >> the xPU. >> > Thanks for investigating this! > > So is this a hardware limitation or something you could change with a > firmware update? Could you move the A2 BAM out of the secure domain and > protect it via the IOMMU instead of the xPU mechanism? The other modern > platforms with IPA do not have this limitation, they can use the IOMMU > for this. > > We can try to support the xPU protection mechanism in the BAM-DMUX > driver, but it's pretty bad from a performance and memory usage point of > view if you need to copy buffers around multiple times. So if you have > some way to change this in the firmware (and there is still time to do > so before production boards ship), I would strongly recommend to > investigate that. > > Thanks, > Stephan I agree that relying on xPU protection in BAM-DMUX introduces performance and memory overheads that would ideally be avoided. I'll dig a bit deeper with the relevant hardware and secure systems teams to understand whether there is any possibility to move A2 BAM behind an IOMMU domain and get back. Thanks, Vishnu