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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by MWH0EPF000A6732.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.139.8 via Frontend Transport; Sun, 14 Jun 2026 16:43:46 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 14 Jun 2026 09:43:35 -0700 Received: from [10.221.208.116] (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 14 Jun 2026 09:43:28 -0700 Message-ID: <4cf4b485-50a3-456b-841c-9625c2beff4b@nvidia.com> Date: Sun, 14 Jun 2026 19:43:24 +0300 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next V3 10/15] net/mlx5: LAG, disable both regular and SD LAG on lag_disable_change To: Tariq Toukan , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Andrew Lunn" , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Mark Bloch , Or Har-Toov , "Edward Srouji" , Maher Sanalla , "Simon Horman" , Gerd Bayer , Kees Cook , Moshe Shemesh , Parav Pandit , Patrisious Haddad , , , , Gal Pressman References: <20260612113904.537595-1-tariqt@nvidia.com> <20260612113904.537595-11-tariqt@nvidia.com> Content-Language: en-US From: Shay Drori In-Reply-To: <20260612113904.537595-11-tariqt@nvidia.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6732:EE_|CY8PR12MB8412:EE_ X-MS-Office365-Filtering-Correlation-Id: a3085bd3-39de-4866-5b95-08deca341a94 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|376014|7416014|23010399003|22082099003|18002099003|4143699003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: xyflI9U+k2CE1ZZ/pjdB9cVEtXcMnhphG+p0ecGsONJERcCVv8uimhUaWL85eeOMjI0L3gaCEPIeoZOr/OuHPE89YoJHYLPdC9imKgSIKXjfDSq+Mzs1I3gXr+XfFGLqLukXuA6YIgY98eeYW7MQwlI7TZO248JY1VBkGsMn0O0T8YvAuDymUOnTqTupqDpp4n60wl0NxR+rguDmfOQWvlFzS5FpjxC2fmDJ5jL/UnS3936D512d7ZPJAduDiSlptk0QjITrbSNwS+9AGfCWUirFyUT8Fs13Botwl2h5jFbtZj8nkdDc+ZW5O0VJJHKcS3L8SKnZ0oIUyAPk7QWjLcZ0qCq5p9BaIeZenBbyB6J4OtMAM6PWap3v9WG1ZXGDJ9IkdcmZ/gp3dMMJ9F5Pmz5e7q8H8Ol0HQLeIsjnAuWPn9ww97V1CS85mXfus2azrB/kNVDfNHQgTiruQakNw8Y9CTZesFLUy/I/IVjpweqZsEHEPIu2gt7s8z87TvuGQiNqbdyh+AmVJZqWSVej5szEcZ6XLhEXsry1kjWwkWx0hgazCNScpoZTvu5JrPTLlRLkyVACgFmj9+iXBYvcUg6MaQZnEYWGth62YlsKLQmjdHErAX6YpCoawggFdjpBqK0jq5KEL90wvJL0AwTrKTNzsymvxFTelxqYePVYyHUXdaZNj/sU4BjezfFyGR5tescvLFpNdYe28aLYTaD9WXqpN9Jk1iPcbaFASQIDcjc= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(376014)(7416014)(23010399003)(22082099003)(18002099003)(4143699003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2IVRrcBKlPNcYE5XjSE0qgRC51UqK4uiQY5Epkq0IMbUyxorZrRXmafkawAKkacMa/+e+jDziIXlez30HKaTTfLO21HEctmG3gz+WAgcMjw79tO555f4t3BS77W4mmrbDbYy3Ml6VPMg5bSN+KlZtV2qy0mv62kwddambR3G2iHMpt9kLR9fgt7pq1n7cHJ3jzEs2lWcCg2E1w8pBmHbbvcgHHsF5fTPMuOEhl2I9pQ7keVQas/yBe5HT2d0EnsDG0yBsEeUkDlkjqFK8a8iZUEa0iTBVpB4h1ekkDQ7PEAEmmBd3rTUrnnw858eFq4xeSfFIfq558wuadgOr85b9sOKCIpjhrM4gXeZsmBlaRfNGaX7ELTLfwnSzhybroctSYGfSeO0r/UCkqTxYpUw01tbgUaDAYPMCeqikyauZr3GcUEQ4J4zCdz+0wuvOYQb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2026 16:43:46.5226 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3085bd3-39de-4866-5b95-08deca341a94 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8412 On 12/06/2026 14:38, Tariq Toukan wrote: > From: Shay Drory > > Extend mlx5_lag_disable_change() to properly disable both regular LAG > and SD LAG when requested. Each LAG type uses its own devcom component > for locking. > > Use mlx5_sd_get_devcom() helper to retrieve the SD devcom component, > needed for proper locking when disabling SD LAG. > > Signed-off-by: Shay Drory > Reviewed-by: Mark Bloch > Signed-off-by: Tariq Toukan > --- > .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 29 +++++++++++++++++-- > 1 file changed, 27 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c > index e23c1e81b98f..84eff995cad1 100644 > --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c > +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c > @@ -2494,13 +2494,22 @@ EXPORT_SYMBOL(mlx5_lag_is_shared_fdb); > > void mlx5_lag_disable_change(struct mlx5_core_dev *dev) > { > + struct mlx5_devcom_comp_dev *sd_devcom = mlx5_sd_get_devcom(dev); > + struct mlx5_core_dev *primary = dev; > struct mlx5_lag *ldev; > + struct lag_func *pf; > + int i; > > ldev = mlx5_lag_dev(dev); > if (!ldev) > return; > > - mlx5_devcom_comp_lock(dev->priv.hca_devcom_comp); > + if (sd_devcom) { > + mlx5_devcom_comp_lock(sd_devcom); > + primary = mlx5_sd_get_primary(dev) ?: dev; > + mlx5_devcom_comp_unlock(sd_devcom); > + } > + mlx5_devcom_comp_lock(primary->priv.hca_devcom_comp); > mutex_lock(&ldev->lock); > > ldev->mode_changes_in_progress++; > @@ -2512,7 +2521,23 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *dev) > } > > mutex_unlock(&ldev->lock); > - mlx5_devcom_comp_unlock(dev->priv.hca_devcom_comp); > + mlx5_devcom_comp_unlock(primary->priv.hca_devcom_comp); > + > + if (!sd_devcom) > + return; > + > + /* Teardown SD shared FDB for this device's group if active */ > + mlx5_devcom_comp_lock(sd_devcom); > + mutex_lock(&ldev->lock); > + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { > + pf = mlx5_lag_pf(ldev, i); > + if (pf->dev == dev && pf->sd_fdb_active) { > + mlx5_lag_shared_fdb_destroy(ldev, pf->group_id); > + break; > + } > + } > + mutex_unlock(&ldev->lock); > + mlx5_devcom_comp_unlock(sd_devcom); sashiko.dev says: Does holding the sd_devcom lock while calling mlx5_lag_shared_fdb_destroy() introduce an AB-BA deadlock with auxiliary device probe? This path acquires sd_devcom, and mlx5_lag_shared_fdb_destroy() eventually reaches mlx5_rescan_drivers_locked() calling device_del() on auxiliary devices, which attempts to acquire device_lock(&adev->dev). This gives us: sd_devcom -> device_lock() However, during auxiliary device probe, the driver core holds device_lock(&adev->dev) before calling mlx5e_probe(). mlx5e_probe() then calls mlx5_sd_get_adev() which acquires sd_devcom, giving us the reverse: device_lock() -> sd_devcom Could the teardown be performed without holding the sd_devcom lock here to prevent this deadlock? [SD] No — the teardown's device_del runs on the IB aux devices, while the device_lock held during probe is the ETH aux device (mlx5e_probe); different struct devices, so no AB-BA > } > > void mlx5_lag_enable_change(struct mlx5_core_dev *dev)