Re: [PATCH 1/5 net-next] tg3: Add 57766 device support.

["Nithin Nayak Sujir" <nsujir@broadcom.com>]

On 02/14/2013 02:25 PM, Joe Perches wrote:
> On Thu, 2013-02-14 at 14:13 -0800, Michael Chan wrote:
>> From: Matt Carlson <mcarlson@broadcom.com>
>>
>> The patch also adds a couple of fixes
>>
>>   - For the 57766, bootcode needs to setup the PCIE Fast Training
>>     Sequence (FTS) value to prevent transmit hangs. Unfortunately, it
>>     does not have enough room in the selfboot case (i.e. devices with no
>>     NVRAM).  The driver needs to implement this.
> []
>> diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
> []
>> @@ -9179,7 +9180,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
>>   		}
>>
>>   		if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
>> -			u32 grc_mode = tr32(GRC_MODE);
>> +			u32 grc_mode;
>> +
>> +			/* Fix transmit hangs */
>> +			val = tr32(TG3_CPMU_PADRNG_CTL);
>> +			val |= TG3_CPMU_PADRNG_CTL_RDIV2;
>> +			tw32(TG3_CPMU_PADRNG_CTL, val);
>> +
>
> This seems to write this val to more devices than just
> a 57766.  Intentional?
>

Yes. In addition to the 57766, this fix applies to non-AX revisions of the 57765.

It's not apparent from the patch, but this code chunk is inside the conditional -

	if (tg3_flag(tp, 57765_CLASS)) {

which is set for 57765 and 57766 devices.



>> +			grc_mode = tr32(GRC_MODE);
>>
>>   			/* Access the lower 1K of DL PCIE block registers. */
>>   			val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
>
>
>