From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE4017C2; Fri, 23 Jun 2023 05:54:36 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F1919D; Thu, 22 Jun 2023 22:54:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687499675; x=1719035675; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=jX5Lr1tAqj4wwCuiTw/iPCwJsi56am7+vbPvNZh5aTg=; b=dKVK6sKgxkjudyEesWIUqT9oTnLbAWoT/YN+x5dUNlOoKktyCmju1wb7 shSnjuDh6K/5pFzSvaKDvOtXUii9gul7tGxJR8fdQKK26e6GB7JYid5JI 6WKQfuojrfebpVf6WLtgPluniDWhBx99oakcefGIqU2LuAuLKT9+Gy4b3 6wItEOI3MWuqfbP3YRkPTYYgueeHgSk+vL926yU4GnuJfLUlT0CNL90G8 y0IgN1afvArTlDwqvdCz2hfPm+UCZHPc+2p74PC+M6phM+UbLGTmPpUeL dbmOYsMvQK1Y7FjC+JYImnFVm23Kbfid7I9prRVWzkfGU7dZuEDO1votm w==; X-IronPort-AV: E=McAfee;i="6600,9927,10749"; a="358186446" X-IronPort-AV: E=Sophos;i="6.01,151,1684825200"; d="scan'208";a="358186446" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2023 22:54:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10749"; a="828251468" X-IronPort-AV: E=Sophos;i="6.01,151,1684825200"; d="scan'208";a="828251468" Received: from choongyo-mobl.gar.corp.intel.com (HELO [10.215.253.116]) ([10.215.253.116]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2023 22:54:24 -0700 Message-ID: <52021da4-c2a5-5350-0a7c-273d76a221c6@linux.intel.com> Date: Fri, 23 Jun 2023 13:54:21 +0800 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC mailbox accessor function and add SoC register access Content-Language: en-US To: Simon Horman Cc: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?UTF-8?Q?Marek_Beh=c3=ban?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan@web.codeaurora.org, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> <20230622041905.629430-2-yong.liang.choong@linux.intel.com> From: Choong Yong Liang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Hi Simon, Yes, you are right. I will add static in v2. Thank you. On 22/6/2023 10:41 pm, Simon Horman wrote: > On Thu, Jun 22, 2023 at 12:19:00PM +0800, Choong Yong Liang wrote: >> From: "David E. Box" >> >> - Exports intel_pmc_core_ipc() for host access to the PMC IPC mailbox >> - Add support to use IPC command allows host to access SoC registers >> through PMC firmware that are otherwise inaccessible to the host due to >> security policies. >> >> Signed-off-by: David E. Box >> Signed-off-by: Chao Qin >> Signed-off-by: Choong Yong Liang > > ... > >> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c >> index da6e7206d38b..0d60763c5144 100644 >> --- a/drivers/platform/x86/intel/pmc/core.c >> +++ b/drivers/platform/x86/intel/pmc/core.c >> @@ -16,6 +16,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -26,7 +27,9 @@ >> #include >> #include >> >> -#include "core.h" >> +#define PMC_IPCS_PARAM_COUNT 7 >> + >> +static const struct x86_cpu_id *pmc_cpu_id; >> >> /* Maximum number of modes supported by platfoms that has low power mode capability */ >> const char *pmc_lpm_modes[] = { > > Hi Choong Yong Liang, > > It looks like pmc_lpm_mode is used in this file and, as of this patch, > has no declaration. Should it be static? > > ... > >> diff --git a/drivers/platform/x86/intel/pmc/core.h b/include/linux/intel_pmc_core.h >> similarity index 95% >> rename from drivers/platform/x86/intel/pmc/core.h >> rename to include/linux/intel_pmc_core.h >> index 9ca9b9746719..82810e8b92a2 100644 >> --- a/drivers/platform/x86/intel/pmc/core.h >> +++ b/include/linux/intel_pmc_core.h >> @@ -250,7 +250,16 @@ enum ppfear_regs { >> #define MTL_LPM_STATUS_OFFSET 0x1700 >> #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C >> >> -extern const char *pmc_lpm_modes[]; >> +#define IPC_SOC_REGISTER_ACCESS 0xAA >> +#define IPC_SOC_SUB_CMD_READ 0x00 >> +#define IPC_SOC_SUB_CMD_WRITE 0x01 >> + >> +struct pmc_ipc_cmd { >> + u32 cmd; >> + u32 sub_cmd; >> + u32 size; >> + u32 wbuf[4]; >> +}; >> >> struct pmc_bit_map { >> const char *name; > > ...